Interconnect Bridge Reference Voltage Stack Noise Reduction
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Solution Overview
Problem
Semiconductor devices face electrical performance limitations due to large power delivery network inductance in multi-chip packages with interconnect bridge applications, leading to increased power supply noise and signaling jitters, making device performance scaling difficult.
Innovation Solution
The implementation of an interconnect bridge within a semiconductor device substrate, coupled between dies, with a reference voltage stack and passive components such as capacitors, inductors, and resistors, which reduces noise by providing a noise reduction function in the power delivery network, enhancing the connection reliability and flexibility of the device configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a large power delivery network is used in multi-chip package with interconnect bridge applications, then power delivery capability is improved, but inductance increases leading to power supply noise
Solution Approach 1:
The power delivery network is segmented into multiple independent power delivery paths distributed across different substrate layers. Each path operates independently with its own reference voltage stack, reducing the inductance loop area for each path while maintaining overall power delivery capability through parallel paths.
Solution Approach 2:
The patent transitions from a planar power delivery network to a three-dimensional structure by stacking reference voltage stacks vertically through multiple substrate layers. This vertical dimensionality reduces the horizontal loop area, thereby reducing inductance and power supply noise while maintaining power delivery capability.
2Object-affected harmful factors
If power delivery network inductance is reduced, then power supply noise is reduced, but device configuration flexibility is limited
Solution Approach 1:
The reference voltage stack structure serves multiple functions simultaneously: it provides voltage reference, acts as a shield against electromagnetic interference, and forms part of the power delivery path. This multi-functionality allows the same structure to reduce noise while supporting various device configurations through flexible interconnect bridge arrangements.
Solution Approach 2:
The patent employs dynamic routing of power and signal paths through the interconnect bridge, allowing the system to adapt configurations based on performance requirements. The reference voltage stacks can be selectively connected to different dies and interconnect bridges, providing flexibility in device configuration while maintaining low inductance paths.
3Reliability
If interconnect bridge is embedded within substrate, then connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The interconnect bridge is nested within the substrate structure, with reference voltage stacks nested through multiple layers. This nesting approach integrates multiple functions into a compact three-dimensional arrangement, improving connection reliability by embedding interconnects within the substrate rather than using surface-mounted connections, while managing manufacturing complexity through systematic layer integration.
Solution Approach 2:
The patent merges the interconnect bridge, reference voltage stacks, and passive components into a single integrated substrate assembly. This consolidation improves connection reliability by reducing the number of separate components and interfaces, while the systematic integration process manages manufacturing complexity through unified fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces noise in the power delivery network, improves device performance, and increases yield by allowing for higher bandwidth and more flexible manufacturing processes, while maintaining a compact design.
Implementation Method 1
The at least one passive component is coupled to two or more levels of the reference voltage stack. In one example, the at least one passive component includes a capacitor.
Data Source
AI summary
A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.