Low Resistance Interconnect via Capping Layer Extraction

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Solution Overview

Problem

The miniaturization of interconnect structures in semiconductor devices leads to increased current density, causing electromigration issues that can result in IC failure, while metallic capping layers used to mitigate this introduce extra resistance and degrade performance.

Innovation Solution

The implementation of a metal wire with a metallic capping layer and a via conductor layer that contacts the metal wire by removing portions of the capping layer, reducing contact resistance and incorporating an insulating layer over the metal wire and capping layer to form the via conductor, thus lowering resistance and signal delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metallic capping layer is used to mitigate electromigration, then reliability is improved, but resistance increases and performance degrades

Engineering Contradiction:

Improveelectromigration resistanceVSAvoidcontact resistance

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent removes portions of the metallic capping layer to form openings, extracting the harmful resistance-introducing portions while retaining the protective function. This allows direct contact between the via conductor and metal wire, eliminating the resistive interface while maintaining electromigration protection in the retained capping layer regions.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The metallic capping layer is selectively removed in specific locations to create openings for via conductors, while retaining the capping layer in other regions. This local modification approach maintains the protective function where needed while eliminating resistance where electrical contact is required.

Inventive Principle:

Principle #3Local quality

2Productivity

If interconnect structures are miniaturized to increase storage capacity and processing speed, then productivity is improved, but current density increases causing electromigration issues

Engineering Contradiction:

Improvestorage capacity and processing speedVSAvoidelectromigration resistance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent uses a composite structure combining metallic capping layer (for electromigration protection) with via conductor material (for low-resistance electrical contact). This composite approach allows the system to simultaneously achieve reliability through the metallic capping layer and low resistance through the via conductor, enabling miniaturization without sacrificing performance.

Inventive Principle:

Principle #40Composite materials

Data Source

PatentUS11476191B2Low resistance interconnect structure for semiconductor device

Publication Date: 2022.10.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure describes an interconnect structure and a method forming the same. The interconnect structure can include a substrate, a layer of conductive material over the substrate, a metallic capping layer over the layer of conductive material, a layer of insulating material over top and side surfaces of the metallic capping layer, and a layer of trench conductor formed in the layer of insulating material and the metallic capping layer.