Interconnect Capping Structure to Prevent Via Loss and IMD Dishing

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Solution Overview

Problem

The formation of interconnect structures in semiconductor devices with high device density and performance is complicated by issues such as via loss and IMD dishing, which affect the reliability and integrity of the metal lines and vias.

Innovation Solution

A capping structure is formed on metal lines using a dielectric material that differs from the inter-metal dielectric material, preventing via loss and IMD dishing by ensuring the top via and capping structure are at the same height and level, thereby stabilizing the interconnect structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a via is formed to connect metal lines in high-density interconnect structures, then connection performance is improved, but via loss and IMD dishing occur reducing reliability

Engineering Contradiction:

Improveinterconnect structure reliabilityVSAvoidinterconnect structure formation complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The capping structure is formed on the metal line before the via is formed, in advance protecting the metal line during subsequent processing steps. This preliminary action prevents via loss and IMD dishing that would otherwise occur during via formation and filling operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The capping structure acts as an intermediary protective layer between the metal line and the via formation process. It mediates the interaction by providing mechanical support and preventing direct damage to the metal line during via etching and filling operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If the capping structure height matches the top via height, then via loss and IMD dishing are prevented, but manufacturing precision requirements increase

Engineering Contradiction:

Improvecapping structure and top via height alignmentVSAvoidinterconnect structure fabrication ease

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The heights of the capping structure and top via are controlled to be substantially equal by adjusting deposition and etching parameters. This parameter control ensures that the planarized surface is formed at the correct level, preventing via loss and IMD dishing while maintaining manufacturability.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentEP4632802A1Semiconductor device including interconnect structure with capping structure

Publication Date: 2025.10.15 SAMSUNG ELECTRONICS CO LTD

Figure 1A
Figure 1B~1C
Figure 2~3

AI summary

Provided is a semiconductor device which includes: a base layer; a 1st metal line on the base layer; a 1st capping structure on the 1st metal line; and an isolation structure surrounding the 1st metal line and the 1st capping structure, wherein the isolation structure and the 1st capping structure comprise different dielectric materials.