Metal Interconnect Cavity Structure for Low Parasitic Capacitance
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Solution Overview
Problem
Front-end-of-line (FEOL) transistors pose a bottleneck in achieving higher density non-volatile memories due to the need for large drive current, which can be addressed by using back-end-of-line (BEOL) transistors as access control devices, but this introduces increased parasitic capacitance due to dielectric structures between word lines and bit/source lines.
Innovation Solution
Incorporating cavities within the dielectric structure in metal interconnects over a substrate, where a first dielectric layer forms a roof, a second dielectric layer forms a base, and a distinct material forms side edges, reducing parasitic capacitance by controlling the height and structure of the cavity to facilitate uniform and stable dielectric layers and improve breakdown voltage for BEOL transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If BEOL transistors are used as access control devices to overcome FEOL transistor limitations, then integration density and memory capacity are improved, but parasitic capacitance increases due to dielectric structures between word lines and bit/source lines
Solution Approach 1:
The patent extracts the problematic dielectric material from the region between word lines and bit/source lines by forming cavities (air gaps) in the interlevel dielectric structure. This removal of dielectric material directly reduces the parasitic capacitance between conductive features while maintaining the BEOL transistor configuration for high integration density.
Solution Approach 2:
The patent introduces cavities (air gaps) into the dielectric structure, creating a porous configuration where air (with near-zero dielectric constant) replaces solid dielectric material. This porous dielectric structure significantly reduces parasitic capacitance between adjacent word lines and bit/source lines, enabling high-density memory implementation with acceptable signal integrity.
2Reliability
If dielectric structures are used between word lines and bit/source lines to provide electrical isolation, then insulation is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by maintaining dielectric material in regions where electrical isolation is critical (such as vertically between metal layers) while removing dielectric material in regions where capacitance reduction is prioritized (horizontally between adjacent word lines and bit/source lines). This selective dielectric placement achieves both insulation and low capacitance objectives.
Solution Approach 2:
The patent creates a porous dielectric structure with cavities that provides electrical isolation through the remaining dielectric material while the air-filled cavities minimize parasitic capacitance. The porous configuration maintains necessary insulation properties while dramatically reducing the harmful capacitive coupling between conductive features.
Data Source
AI summary
An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.