Mitigating Interconnect Variability via CMP Density Estimation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Interconnect variability in integrated circuits during the design stage, caused by Chemical-Mechanical Polishing (CMP) processes, leads to mismatch between design and manufacturing, affecting performance and manufacturability, as existing techniques like dummy fills and cheesing holes are applied post-design and have limitations in compensating for metal density variations and timing closure issues.
Innovation Solution
A method that involves global and detailed routing of interconnects, dummy fill estimation, grid-based metal density estimation, and obtaining a variable map of metal thicknesses to identify sensitive wiring nets, which are then re-routed for optimization, thereby mitigating interconnect variability during the design stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy fills are inserted in low density regions to equalize spatial density, then layout density evenness is improved, but interconnect signal delay and crosstalk are affected due to resistance and coupling capacitance changes
Solution Approach 1:
The patent performs dummy fill estimation and metal density estimation during the design stage, before final layout completion. This preliminary action allows the routing process to anticipate density issues and adjust wire routing accordingly, rather than applying dummy fills as a post-processing step that inadvertently affects signal characteristics.
Solution Approach 2:
The patent changes the routing parameters (wire thickness, routing paths) based on predicted metal density variations from CMP. By adjusting routing parameters proactively based on density predictions, the system compensates for expected CMP variability without relying on dummy fills that would alter resistance and capacitance.
2Manufacturing precision
If holes are formed on wide wires to reduce metal density, then layout density evenness is improved, but interconnect signal delay and crosstalk are affected due to resistance and coupling capacitance changes
Solution Approach 1:
The patent performs metal density estimation and identifies regions requiring density reduction before final routing completion. This allows the routing process to proactively avoid creating high-density regions that would require cheesing, rather than forming holes as a post-processing step that degrades signal characteristics.
Solution Approach 2:
The patent adjusts routing parameters (wire thickness, routing paths) based on predicted metal density variations. By changing routing parameters proactively, the system prevents the formation of high-density regions that would require holes to be formed, thereby avoiding the signal degradation associated with cheesing.
3Manufacturing precision
If post-design processes are used to compensate for metal density variation, then layout density evenness is improved, but design flexibility is reduced since the design is already fixed
Solution Approach 1:
The patent integrates dummy fill estimation and metal density estimation into the design stage workflow, performing these operations before the design is finalized. This preliminary action maintains design flexibility by allowing routing adjustments based on predicted CMP variability, rather than being constrained by a fixed design that requires post-processing compensation.
4Manufacturing precision
If CMP process is used for planarization, then reliable multilevel copper interconnects are established, but metal thickness variation occurs affecting timing closure
Solution Approach 1:
The patent changes routing parameters (wire thickness, routing paths) based on predicted metal density variations from CMP. By adjusting these parameters proactively during design, the system compensates for expected CMP-induced thickness variations, ensuring timing closure is achieved despite the planarization process variability.
Solution Approach 2:
The patent uses a feedback loop where metal density estimation informs routing decisions. The estimated density map from CMP modeling feeds back into the routing process, allowing the system to adjust routing parameters based on predicted outcomes, thereby compensating for CMP variability and ensuring timing closure.
Data Source
AI summary
The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.