Interconnect Structure Layout to Reduce CMP Dishing
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Solution Overview
Problem
The existing semiconductor manufacturing techniques face challenges in reducing the dishing phenomenon in low device density regions or large linewidth regions during the polishing process of interconnect structures, which affects the quality of the interconnects.
Innovation Solution
The introduction of a dielectric layer with protrusions that are strategically arranged to intersect any straight path crossing the central region, effectively blocking the dishing path and reducing the dishing phenomenon by distributing protrusions in a pattern that includes bent strips and straight bars, and slots, which are designed to resist polishing pressure uniformly across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the polishing process is performed on the substrate, then the copper material is planarized, but the copper in the low device density regions experiences greater polishing pressure and suffers from dishing
Solution Approach 1:
The patent introduces protrusions with different heights in the dielectric layer to create local variations in structure. The first protrusions have a first height and the second protrusions have a second height different from the first height. This local quality differentiation allows the structure to resist polishing pressure more effectively in low device density regions, preventing dishing while maintaining planarization in other areas.
Solution Approach 2:
The protrusions are formed in the dielectric layer before the copper material is deposited and before the polishing process occurs. This preliminary action of creating the protrusion structure anticipates the polishing pressure that will be applied, allowing the structure to be pre-configured to resist dishing during the subsequent polishing process.
2Ease of manufacture
If the copper material covers the pattern of the dielectric layer with greater linewidth in low device density regions, then the interconnect structures are formed, but the greater linewidth causes dishing during polishing
Solution Approach 1:
The patent applies local quality by creating protrusions at specific locations within the dielectric layer, particularly in low device density regions where dishing is most problematic. The protrusions have different heights (first height and second height) to provide localized reinforcement where needed, allowing the copper material to maintain its greater linewidth for ease of manufacture while the protrusions prevent dishing during polishing.
Solution Approach 2:
The dielectric layer is segmented into regions with and without protrusions, and the protrusions themselves are divided into different height levels. This segmentation allows the structure to be optimized locally - the first protrusions provide one level of resistance to polishing pressure while the second protrusions provide a different level, creating a graduated defense against dishing in the low device density regions.
Data Source
AI summary
An interconnect structure is formed on a substrate in a semiconductor device. The interconnect structure includes a dielectric layer and a metal layer. The dielectric layer includes a region and a plurality of protrusions. The metal layer is disposed on the region and between the protrusions, wherein tops of the protrusions are exposed with respect to the metal layer. In a top view of the semiconductor device, the protrusions are distributed in the region. Any straight path crossing through a central region of the region is always intersected with a portion of the protrusions.