Semiconductor Interconnect Structure With CMP Stop Layer for Via Integrity
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, challenges arise in maintaining the integrity of conductive features during planarization processes, leading to issues like dishing or erosion of metallization layers and conductive vias, which affect the integration density and reliability of electronic components.
Innovation Solution
The implementation of a combined etch stop layer and CMP stop layer, made from specific dielectric materials, which aids in forming through substrate vias and conductive interconnects while preventing dishing or erosion by controlling the planarization process and ensuring uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planarization process is performed to achieve flat surface for subsequent lithography, then surface uniformity is improved, but conductive features such as metallization layers and conductive vias suffer from dishing or erosion
Solution Approach 1:
An etch stop layer is introduced as an intermediary layer between the conductive features and the CMP process. This layer acts as a sacrificial mediator that protects the conductive features from erosion and dishing during planarization, while still allowing the CMP process to achieve the required surface uniformity for subsequent lithography steps.
Solution Approach 2:
The etch stop layer is deposited beforehand to provide cushioning protection to the conductive features before the CMP process begins. This pre-positioned protective layer absorbs the mechanical stress and chemical action of the CMP process, preventing direct damage to the underlying conductive structures.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but additional process problems arise that affect manufacturing precision
Solution Approach 1:
The etch stop layer enables parameter changes in the CMP process by providing a controlled removal rate interface. This allows the CMP process to be optimized for surface uniformity without compromising the dimensional integrity of miniaturized conductive features, thereby maintaining manufacturing precision even as feature sizes are reduced to increase integration density.
3Manufacturing precision
If CMP process is performed to achieve flat surface, then surface uniformity is improved, but conductive features experience dishing or erosion
Solution Approach 1:
The etch stop layer serves as a protective intermediary that sits between the CMP abrasives and the conductive features. During the CMP process, this layer is selectively removed to achieve surface flatness while its presence during the process prevents direct contact between the CMP slurry and the conductive features, thereby preventing dishing and erosion of their shapes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively integrates process steps for forming interconnect structures, preventing dishing or erosion of conductive features and enhancing the integration density and reliability of semiconductor devices by maintaining the integrity of metallization layers and conductive vias.
Implementation Method 1
performing a planarization process on the conductive material to expose the second dielectric layer
Implementation Method 2
forming a through via within the first dielectric layer, the second dielectric layer and the substrate
Data Source
AI summary
A semiconductor device includes a substrate. A first dielectric layer is over the substrate. A first interconnect is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and the first interconnect. A conductive via extends through the first dielectric layer, the second dielectric layer and the substrate. A topmost surface of the conductive via is level with a topmost surface of the second dielectric layer. A third dielectric layer is over the second dielectric layer and the conductive via. A fourth dielectric layer is over the third dielectric layer. A second interconnect is in the fourth dielectric layer. The second interconnect extends through the third dielectric layer and the second dielectric layer and physically contacts the first interconnect.