Interconnects with Conductive Posts Through Intermediate Circuitry
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Solution Overview
Problem
Existing methods for forming electrical interconnections through densely patterned intermediate levels in semiconductor constructions often damage circuitry, consume valuable semiconductor real estate, and fail to adequately protect the intermediate level, leading to device performance issues and potential failure.
Innovation Solution
The method involves forming interconnects using a hard mask to define a location within the densely patterned region, eliminating the need for dummy features, and creating multiple electrically conductive posts that extend through the intermediate level without damaging existing conductive features, allowing for direct electrical connections between circuitry levels while maintaining the integrity of the intermediate level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If openings are etched through dummy features to provide paths for electrical interconnections, then electrical interconnection paths are created, but valuable semiconductor real estate is consumed and the intermediate level is not adequately protected
Solution Approach 1:
The patent extracts and removes the dummy features from the fabrication process entirely. Instead of using dummy features as placeholders, the method directly forms openings through the intermediate level at precisely defined locations using a hard mask, thereby eliminating the waste of semiconductor real estate while maintaining reliable electrical interconnections.
Solution Approach 2:
The hard mask is formed in advance at the precise location where the opening is needed, before any etching occurs. This preliminary positioning ensures that the opening is created exactly where required without consuming additional semiconductor area, and the hard mask protects the surrounding intermediate level circuitry during the etching process.
2Reliability
If circuit pattern is broken within intermediate level to create path for electrical interconnection, then electrical interconnection is achieved, but circuitry within intermediate level is damaged
Solution Approach 1:
The hard mask serves as an intermediary protective layer during the opening formation process. It is precisely positioned at the interconnection location and protects the surrounding intermediate level circuitry from etching damage, allowing the opening to be created without breaking or damaging the existing circuit pattern.
Solution Approach 2:
The hard mask provides localized protection only at the specific location where the opening is needed, rather than requiring dummy features across the entire intermediate level. This localized approach ensures that the circuit pattern remains intact everywhere except at the precise interconnection point, eliminating harmful damage to the circuitry.
3Ease of manufacture
If dummy features are formed along intermediate level, then interconnection paths can be created, but fabrication process complexity increases and real estate is consumed
Solution Approach 1:
The patent removes the dummy feature step from the fabrication process entirely. The hard mask is formed directly at the required opening location using standard photolithography and etching techniques, eliminating the need for separate dummy feature formation, modification, and removal steps, thereby simplifying the overall fabrication process.
Solution Approach 2:
The hard mask is formed in advance at the precise location where the opening is needed, consolidating the positioning and protection functions into a single step. This eliminates the need for subsequent dummy feature manipulation steps, reducing fabrication process complexity while maintaining ease of manufacture for creating interconnection paths.
Data Source
AI summary
Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.