Interconnect Cross-Section Design for Thermal Stress Relief
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Solution Overview
Problem
Semiconductor devices with interconnects spanning different base materials with varying coefficients of linear expansion are prone to stress and potential breakage due to thermal expansion differences, leading to reliability issues.
Innovation Solution
The interconnects are designed with a greater cross-sectional area at the boundary region between base materials, and can include widening portions or branching configurations to enhance strength and reduce the likelihood of breakage, even under thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an interconnect is formed over base materials with different coefficients of linear expansion to straddle the borderline between them, then the number of terminals can be increased (fan out WLP configuration), but the interconnect becomes prone to stress and breakage due to thermal expansion differences
Solution Approach 1:
The interconnect is designed with a non-uniform cross-sectional area, specifically with a widened portion at the boundary region between the first and second base materials. This local modification increases the cross-sectional area precisely where thermal stress is most concentrated, providing enhanced strength and stress distribution at the critical interface while maintaining the overall interconnect structure.
Solution Approach 2:
The cross-sectional area parameter of the interconnect is changed along its length, with a specific increase at the boundary region. This parameter modification allows the interconnect to withstand thermal expansion differences by providing a larger cross-sectional area where stress is most severe, thereby improving reliability without affecting the terminal count.
2Reliability
If the cross-sectional area of the interconnect is increased at the boundary region to reduce stress, then the reliability improves, but the interconnect density may be reduced
Solution Approach 1:
The interconnect maintains a standard cross-sectional area in most regions to preserve density, but introduces a localized widened portion only at the boundary region between different base materials. This targeted approach provides the necessary stress relief and reliability improvement precisely where thermal expansion differences cause maximum stress, while keeping the rest of the interconnect compact and dense.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves the reliability of semiconductor devices by reducing the risk of interconnect failure due to thermal expansion mismatches, maintaining interconnect density, and ensuring electrical continuity.
Implementation Method 1
Materials forming a semiconductor device have a coefficient of linear expansion (CLE) specific to heat. When the temperature of a semiconductor device has changed, the amounts of expansion or contraction of materials having different CLEs are different from each other. This difference induces a strain at the interface at which the materials having different CLEs are in contact with each other.
Data Source
AI summary
A semiconductor device includes a first base material having a first surface; a second base material having a coefficient of linear expansion different from that of the first base material, being in contact with the first base material, and having a second surface being adjacent to the first surface; and a first interconnect formed over the first and second surfaces to straddle a borderline between the first and second base materials. The cross-sectional area of the first interconnect along the borderline is greater than the cross-sectional area of at least part of a portion of the first interconnect on the first surface along a width of the first interconnect, or the cross-sectional area of at least part of a portion of the first interconnect on the second surface along the width of the first interconnect.