Electronic Interconnect Delay Bound Determination Using Virtual Flow Controllers

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Solution Overview

Problem

Modern integrated circuits face challenges in determining delay bound parameters for electronic interconnects, particularly in systems with wormhole-type switches, which can lead to inefficiencies in design and potential over-design to ensure quality of service (QOS) compliance due to the complexity of routing latencies and congestion.

Innovation Solution

A method is introduced to determine delay bound parameters by analyzing performance guarantees for electronic interconnects, involving the conversion of wormhole-type signal paths into feed-forward FIFO signal paths, using service curves and virtual flow controllers to simplify the analysis and ensure deterministic calculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wormhole-type switches are used in electronic interconnects, then routing flexibility and throughput are improved, but determining delay bound parameters becomes complex and inaccurate

Engineering Contradiction:

ImprovethroughputVSAvoiddelay bound parameter accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The patent introduces virtual flow controllers as intermediary components that regulate traffic flow between switches and networks. These virtual flow controllers enable deterministic delay bound calculations by controlling the timing and flow of packets, thereby resolving the complexity in measuring delay parameters in wormhole-switched networks while maintaining high throughput

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If conventional analysis methods are used for electronic interconnects, then design process is simpler, but QOS compliance cannot be guaranteed due to routing latency complexity

Engineering Contradiction:

Improvedesign simplicityVSAvoidQOS compliance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent transforms the complex wormhole switching model into an equivalent FIFO (first-in-first-out) queuing model by changing the analysis parameters. This parameter transformation allows designers to use simple conventional analysis methods while obtaining accurate delay bound parameters that guarantee QOS compliance, thus achieving both design simplicity and reliability

Inventive Principle:

Principle #35Parameter changes

3Reliability

If over-design is performed to ensure QOS compliance, then reliability is improved, but system efficiency decreases due to resource wastage

Engineering Contradiction:

ImproveQOS complianceVSAvoidsystem efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent replaces conservative over-design approaches with precise analytical models that calculate exact delay bound parameters. By substituting the mechanical trial-and-error over-design process with a mathematical analysis model, the system achieves QOS compliance without unnecessary resource allocation, thereby maintaining high system efficiency while ensuring reliability

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11455268B2Method, system and device for electronic interconnect delay bound determination

Publication Date: 2022.09.27 ARM LTD

AI summary

The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.