Interconnect Die Stacking for High-Bandwidth Embedded Memory Access
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Solution Overview
Problem
Accessing memory in computing systems is slow due to the separation of processor and memory dies, which limits computational performance.
Innovation Solution
An interconnect die is introduced between logic dies stacked over a base die with embedded memory, enabling hybrid bonding and direct, high-speed access to the embedded memory through a configuration with tighter metal pitch and more vertical interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If processor and memory are separated onto different dies, then integration density is improved, but memory access speed deteriorates
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional stacked architecture, placing memory and processor on different vertical levels connected through vertical interconnects (TSVs). This dimensional change enables both high integration density through stacking and fast access through direct vertical pathways, resolving the contradiction between density and speed.
Solution Approach 2:
The patent introduces an interconnect die with buffer memory as an intermediary component between the processor die and embedded memory. This intermediary enables faster access by providing local caching and reducing the critical path delay, while maintaining the benefits of separated processor and memory dies for high integration density.
2Speed
If processor and memory are integrated on the same die, then memory access speed is improved, but integration density deteriorates
Solution Approach 1:
The patent segments the system into multiple specialized dies (processor die, memory die, interconnect die) stacked vertically. Each die is optimized for its specific function, allowing the memory die to be accessed rapidly through direct vertical interconnects while the processor die maintains high computational density. This segmentation resolves the contradiction by achieving both fast access and high overall integration density through 3D stacking.
3Quantity of substance
If hybrid bonding is used to stack dies, then interconnect density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary alignment marks and bonding pads designed specifically for hybrid bonding processes. These pre-configured features enable precise alignment and robust bonding between stacked dies, reducing manufacturing complexity despite the advanced bonding technique required to achieve high interconnect density.
Data Source
AI summary
Examples of integrated circuit (IC) devices including an interconnect die between logic dies stacked over a base die with embedded memory may enable ultra-high bandwidth memory access. In one example, an IC device includes an interposer (e.g., a die or base die) including embedded memory, a first die (for example, a die including home agent logic) over the interposer, where the first die is hybrid bonded with the interposer. The IC device includes a second die (e.g., a chiplet, compute die, etc.) over the first die. The IC device includes a third die (e.g., an interconnect die) between the first die and the second die, where the third die includes a plurality of interconnect layers and is hybrid bonded with the first die and the second die. In one example, devices in device regions of the first die and second die are coupled via conductive interconnects in the interconnect die.