Interconnect Dielectric Crack Stop for Advanced Nodes

Solution Overview

Problem

As semiconductor technologies scale down to 14 nm, 10 nm, and beyond, the small via sizes in crack stop regions fail to provide adequate toughness, leading to crack stop breaches and chip failure due to the poor mechanical strength and moisture insulation of low-k interconnect dielectric materials during wafer cutting and bonding processes.

Innovation Solution

An interconnect level is designed with a crack stop region surrounding the wiring region, using a dielectric material with a higher dielectric constant than the interconnect dielectric material, which may or may not include a metallic structure, to enhance crack stop capability and prevent crack propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If low-k interconnect dielectric material is used to minimize parasitic capacitances, then electrical performance is improved, but mechanical strength and moisture insulation deteriorate causing crack formation during wafer cutting and bonding

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidmechanical strength

Core Design Contradiction:

Loss of energyVSStrength

Solution Approach 1:

The interconnect structure is divided into two distinct regions: a wiring region filled with low-k dielectric material for optimal electrical performance, and a crack stop region filled with high-k dielectric material for mechanical strength and crack prevention. This segmentation allows each region to have optimized properties for its specific function without compromising the other.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different dielectric materials with different properties are applied to different locations within the interconnect structure. The wiring region uses low-k material for minimal parasitic capacitance, while the crack stop region uses high-k material for enhanced mechanical strength and moisture insulation. This local differentiation resolves the contradiction by allowing optimal properties in each specific location.

Inventive Principle:

Principle #3Local quality

2Loss of energy

If low-k interconnect dielectric material is used, then electrical performance is improved, but moisture insulation deteriorates leading to chip failure

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidmoisture insulation

Core Design Contradiction:

Loss of energyVSObject-affected harmful factors

Solution Approach 1:

The interconnect structure is divided into two distinct regions: a wiring region filled with low-k dielectric material for optimal electrical performance, and a crack stop region filled with high-k dielectric material for mechanical strength and crack prevention. This segmentation allows each region to have optimized properties for its specific function without compromising the other.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different dielectric materials with different properties are applied to different locations within the interconnect structure. The wiring region uses low-k material for minimal parasitic capacitance, while the crack stop region uses high-k material for enhanced mechanical strength and moisture insulation. This local differentiation resolves the contradiction by allowing optimal properties in each specific location.

Inventive Principle:

Principle #3Local quality

3Productivity

If via sizes are reduced to meet scaling requirements at 14 nm, 10 nm, and below, then device density is improved, but crack stop toughness decreases resulting in crack stop breach

Engineering Contradiction:

Improvedevice densityVSAvoidcrack stop toughness

Core Design Contradiction:

ProductivityVSStrength

Solution Approach 1:

The patent applies different dielectric materials to different regions: the wiring region uses low-k material for electrical performance, while the crack stop region uses high-k material specifically to provide enhanced toughness and prevent crack propagation. This local differentiation allows via sizes to be reduced for higher device density while the high-k crack stop region maintains sufficient toughness to prevent crack stop breach.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The interconnect structure employs a composite approach by combining low-k dielectric material in the wiring region with high-k dielectric material in the crack stop region. This composite structure allows the system to simultaneously achieve the electrical benefits of low-k material and the mechanical benefits of high-k material, enabling scaled via sizes without compromising crack stop capability.

Inventive Principle:

Principle #40Composite materials

Data Source

PatentUS10964647B2Dielectric crack stop for advanced interconnects

Publication Date: 2021.03.30 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

An interconnect level is provided on a surface of a substrate that has improved crack stop capability. The interconnect level includes at least one wiring region including an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region laterally surrounding the wiring region. The crack stop region includes a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material. The crack stop region may be devoid of any metallic structure, or it may contain a metallic structure. The metallic structure in the crack stop region, which is embedded in the crack stop dielectric material, may be composed of a same, or different, electrically conductive metal or metal alloy as the electrically conductive structure embedded in the interconnect dielectric material.