Semiconductor Interconnect Dielectric Spacers
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Solution Overview
Problem
The reduction of parasitic capacitances in semiconductor interconnect structures is hindered by the presence of etch stop and glue layers, which can lead to increased inter/intra parasitic capacitances and misalignment issues during the formation of conductive structures, affecting the reliability and performance of the interconnects.
Innovation Solution
The formation of dielectric spacers on the sidewalls of conductive structures within the interconnects, which act as etch stop layers and reduce the risk of damage during the etching process, thereby minimizing parasitic capacitances and misalignment-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etch stop layer and glue layer are formed over the dielectric layer, then the conductive structures can be formed with proper etching control, but the inter/intra parasitic capacitances between adjacent conductive structures increase
Solution Approach 1:
The patent removes the traditional etch stop layer and glue layer from the interconnect structure. Instead, dielectric spacers are formed only on the sidewalls of the cap portion of conductive structures, extracting the harmful dielectric layers while maintaining etching control through the spacer structures.
Solution Approach 2:
Dielectric spacers are introduced as intermediary structures formed on the sidewalls of conductive structures. These spacers serve as the etch stop function previously provided by separate layers, while minimizing parasitic capacitance by being localized only where needed for etching control.
2Object-generated harmful factors
If etch stop layer and glue layer are removed to reduce parasitic capacitances, then the parasitic capacitances decrease, but misalignment issues and damage to underlying dielectric layer occur during etching
Solution Approach 1:
Dielectric spacers are formed preliminarily on the sidewalls of conductive structures before the etching of the overlying dielectric layer. This preliminary placement of spacers ensures proper etching control and prevents misalignment and damage to the underlying dielectric layer, while still maintaining low parasitic capacitance.
Solution Approach 2:
Instead of using continuous etch stop and glue layers across the entire structure, dielectric spacers are applied locally only on the sidewalls of the cap portion of conductive structures. This localized approach provides etching protection exactly where needed while minimizing the overall dielectric material present, thus reducing parasitic capacitances.
3Manufacturing precision
If traditional multi-layer interconnect structure with etch stop and glue layers is used, then the conductive structures can be formed, but the device complexity and manufacturing steps increase
Solution Approach 1:
The patent combines the etch stop function and the sidewall protection function into a single dielectric spacer structure formed on the cap portion of conductive structures. This merging eliminates the need for separate etch stop layer and glue layer, reducing device complexity and manufacturing steps while maintaining proper conductive structure formation.
Solution Approach 2:
The patent extracts and removes the redundant etch stop layer and glue layer from the traditional multi-layer interconnect structure. The essential function of these layers is retained through the dielectric spacers formed only on the sidewalls of cap portions, simplifying the overall structure and reducing manufacturing complexity.
Data Source
AI summary
A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.