Interconnect Dielectric Voids for Lower Parasitic Capacitance
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Solution Overview
Problem
The scaling down of transistor dimensions in electronic devices leads to increased capacitive coupling and parasitic capacitance between adjacent conductive features, negatively impacting device speed and performance.
Innovation Solution
A method for fabricating an integrated circuit structure that involves forming conductive features with a protection layer and a dielectric layer with voids between them, using processes like chemical vapor deposition and etching, to reduce capacitance while minimizing damage to the conductive features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent conductive features is decreased to increase transistor density, then the number of transistors per device increases, but the parasitic capacitance between adjacent conductive features increases
Solution Approach 1:
The patent removes the dummy dielectric material from between adjacent conductive features, extracting the harmful capacitive coupling element. This creates air gaps that eliminate the parasitic capacitance caused by the dummy dielectric, while maintaining the close spacing needed for high transistor density
Solution Approach 2:
The patent introduces a porous low-k dielectric material to replace the solid dummy dielectric. This porous structure has lower effective permittivity, reducing the parasitic capacitance between adjacent conductive features while still providing dielectric support and maintaining mechanical integrity
2Object-generated harmful factors
If dummy dielectric material is removed to reduce capacitance, then parasitic capacitance decreases, but damage to conductive features increases
Solution Approach 1:
The patent forms a protective coating on the conductive features before removing the dummy dielectric material. This preliminary protective layer prevents damage to the conductive features during the subsequent dummy dielectric removal process, ensuring feature integrity while allowing capacitance reduction
Solution Approach 2:
The patent introduces a protective coating as an intermediary layer between the dummy dielectric and the conductive features. This mediator protects the conductive features from direct exposure to the removal process, preventing damage while enabling the dummy dielectric to be removed for capacitance reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhances device performance, and maintains the structural integrity of conductive features by forming voids between adjacent conductive features within the dielectric layer, thereby alleviating the need for additional photolithographic masking and etching operations.
Implementation Method 1
when the distance between the adjacent conductive features decreases, the resulting capacitance of the dielectric material increases, which results in increased parasitic capacitance
Implementation Method 2
using processes like chemical vapor deposition and etching
Data Source
AI summary
An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.