Interconnect Structure Patterning With Dual Resist Line and Pillar Masks
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Solution Overview
Problem
Conventional methods for forming interconnect structures in integrated circuits, such as the dual damascene and semi-damascene processes, are inefficient due to the need for multiple lithography and etching steps, which can be improved by using a dual resist layer approach to enable more efficient formation of horizontal metal lines and vertical metal vias.
Innovation Solution
A method involving the use of two resist layers of different materials, where the second resist layer is used as an etch mask for the first resist layer to define a hard mask line pattern and subsequently a metal line pattern, allowing for the formation of metal pillars on top of the metal lines without the need for via holes, thereby reducing the number of lithography and etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the conventional semi-damascene process is used, then the need for CMP of the metal layer is removed, but two separate lithography and etching process steps are required
Solution Approach 1:
The patent combines two separate lithography and etching processes into a single integrated process. The first resist pattern defines via hole locations, and the second resist pattern defines metal line locations. Both patterns are etched simultaneously through the dielectric layer and metal layer in one etching step, eliminating the need for two separate litho-etch sequences while maintaining the benefit of removing the CMP step.
Solution Approach 2:
The patent segments the patterning process into two distinct resist layers, each serving a specific function. The first resist material patterns the via holes, while the second resist material patterns the metal lines. This segmentation allows each resist to be optimized for its specific purpose and enables simultaneous etching of both features in a single process step.
2Reliability
If via holes are filled with metal before etching metal lines, then via connections are formed, but the process requires sequential lithography and etching steps
Solution Approach 1:
The patent performs preliminary patterning of both via holes and metal lines using two separate resist layers before the actual etching step. The first resist pattern establishes the via hole locations, and the second resist pattern establishes the metal line locations. This preliminary segmentation allows the subsequent etching step to efficiently create both features simultaneously, improving productivity while ensuring reliable via connections.
Solution Approach 2:
The patent uses two different resist materials as intermediaries to transfer the desired patterns to the underlying layers. The first resist material serves as an intermediary for via hole patterning, and the second resist material serves as an intermediary for metal line patterning. These resist intermediaries enable the simultaneous definition of both via and line patterns, allowing efficient single-step etching while maintaining pattern fidelity and connection reliability.
Data Source
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AI summary
According to an aspect, there is provided a method for forming an interconnect structure for an integrated circuit, comprising: forming a metal layer over a substrate; forming a hard mask layer over the metal layer; forming a first resist layer of a first resist material over the hard mask layer and patterning the first resist layer in a first lithography process to define a first resist pattern; forming over the first resist pattern a second resist layer of a second resist material different from the first resist material and patterning the second resist layer in a second lithography process to define a second resist pattern of resist lines extending in parallel along a first direction, wherein at least a portion of the first resist pattern is overlapped by the second resist pattern; patterning the hard mask layer using the second resist pattern as an etch mask to define a hard mask line pattern underneath the second resist pattern, and subsequently the metal layer to define a metal line pattern underneath the hard mask line pattern; removing the second resist pattern and subsequently patterning the hard mask line pattern using said at least a portion of the first resist pattern as an etch mask to define a hard mask pillar pattern over the metal line pattern; and forming a metal pillar pattern in accordance with the hard mask pillar pattern.