Interconnect-Embedded Ion-Sensitive Transistors for Simpler BEOL Sensing
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Solution Overview
Problem
Existing ion-sensitive transistors used for life-science applications face challenges in manufacturing complexity and cost, particularly when integrating sensing layers during back-end-of-line processes in semiconductor devices.
Innovation Solution
Embedding sensor components, such as thin film transistors with indium gallium zinc oxide channels and high-k dielectric gates, within interconnects during back-end-of-line processes simplifies manufacturing and reduces costs by integrating them during standard semiconductor fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ion-sensitive transistors are integrated during back-end-of-line processes, then sensing functionality is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the ion-sensitive transistor fabrication with standard semiconductor interconnect processes. The transistor channel is formed within the interconnect structure itself, combining what were previously separate manufacturing steps into a unified process flow, thereby reducing overall manufacturing complexity while maintaining sensing functionality
Solution Approach 2:
The interconnect structure serves dual purposes: it functions as both the electrical interconnect and as the transistor channel formation region. This multi-functionality eliminates the need for separate transistor fabrication steps, reducing manufacturing complexity while achieving the desired sensing capability
2Adaptability or versatility
If ion-sensitive transistors are integrated during back-end-of-line processes, then sensing functionality is achieved, but manufacturing cost increases
Solution Approach 1:
By merging transistor fabrication with standard interconnect processes, the patent eliminates redundant manufacturing steps and reduces the need for specialized equipment, thereby lowering overall manufacturing cost while maintaining sensing functionality
Solution Approach 2:
The standard semiconductor fabrication process serves the dual purpose of creating both interconnects and ion-sensitive transistors. The existing process infrastructure and materials are utilized to create the sensing functionality, eliminating the need for separate specialized manufacturing lines and reducing costs
3Ease of manufacture
If sensor components are embedded within interconnects, then manufacturing is simplified, but device structure becomes more complex
Solution Approach 1:
The transistor channel structure is nested within the interconnect structure itself. The channel formation regions are embedded within the interconnect pathways, creating a compact integrated structure that simplifies manufacturing while the nested arrangement manages structural complexity through hierarchical organization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach lowers manufacturing costs and simplifies the process of creating ion-sensitive transistors for life-science applications by leveraging existing semiconductor fabrication techniques, enhancing their integration and reducing complexity.
Implementation Method 1
thin film transistors with indium gallium zinc oxide channels
Implementation Method 2
high-k dielectric gates
Data Source
AI summary
A semiconductor device includes a substrate, an interconnect, a second transistor, and a sensing film. The substrate includes devices disposed therein. The interconnect is disposed on the substrate and electrically coupled to the devices, where the interconnect includes a plurality of build-up layers and a through hole formed therein. The first transistor is disposed in the interconnect and vertically extends through at least one of the plurality of build-up layers, and the first transistor is electrically coupled to a first device of the devices through the interconnect. The second transistor is disposed in the interconnect and vertically extends through the at least one of the plurality of build-up layers, and the second transistor is electrically coupled to a second device of the devices through the interconnect, where the first transistor and the second transistor are laterally separated from one another through the through hole. The sensing film is disposed on the interconnect and further extends into the through hole, where the sensing layer is laterally disposed between the first transistor and the second transistor.