Interconnect Opening Etch Sequence for Residue and Oxide Removal
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Solution Overview
Problem
The formation of interconnect structures in semiconductor devices is hindered by residual materials and native oxides, which increase contact resistance, void formation, and etch rate issues, leading to decreased yield and performance, and require multiple processing steps and chamber transfers that increase equipment costs and expose devices to adverse conditions.
Innovation Solution
A multi-step etch process involving multiple dry etching operations with wet cleaning in between, and performing dry ashing in the same chamber as the first dry etching operation to effectively remove residual materials and native oxides, reducing the need for multiple chamber transfers and environmental exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple processing steps and chamber transfers are used to remove residual materials and native oxides, then cleaning effectiveness is improved, but equipment cost increases and devices are exposed to adverse conditions
Solution Approach 1:
The patent combines multiple processing functions (dry etching, wet cleaning, and dry ashing) into a single integrated processing chamber. The chamber is configured with multiple process zones that can sequentially perform different operations without requiring chamber transfers, thereby maintaining cleaning effectiveness while reducing equipment complexity and environmental exposure risks
Solution Approach 2:
The processing chamber is designed as a multi-functional system capable of performing dry etching, wet cleaning, and dry ashing operations within the same chamber. This universal chamber eliminates the need for multiple specialized chambers, reducing overall system complexity while maintaining the effectiveness of each individual process
2Ease of manufacture
If residual materials and native oxides are not removed, then processing is simpler, but contact resistance increases and yield decreases
Solution Approach 1:
The patent performs preliminary cleaning actions (wet cleaning and dry ashing) within the same processing chamber before final interconnect formation. This preliminary removal of residual materials and native oxides prevents contact resistance issues and yield loss, while the integrated chamber design maintains processing simplicity by eliminating the need for separate cleaning equipment
3Reliability
If chamber transfers are performed between processing steps, then process specialization is improved, but devices are exposed to adverse environmental conditions
Solution Approach 1:
The patent merges multiple processing steps (dry etching, wet cleaning, dry ashing) into a single continuous process within one chamber. This eliminates chamber transfers and the associated environmental exposure risks, while the chamber is designed to maintain process quality through controlled conditions and sequential process zones
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of interconnect structures, reduces under etching, and increases semiconductor device yield and performance by effectively removing residual materials and native oxides, while minimizing processing time and equipment costs.
Implementation Method 1
a first plasma-based dry etching process is performed to form an opening in the semiconductor device
Implementation Method 2
A wet cleaning process is performed to remove residual materials and native oxides from the opening
Implementation Method 3
a second plasma-based dry etching process is performed to form the opening through the dielectric layer and the etch stop layer to expose a top surface of the metal capping layer
Data Source
AI summary
Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.