Etch Stop Layer for Interconnect Depth Control

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Solution Overview

Problem

Conventional dual- and single-damascene processes for forming interconnect structures in integrated circuits face challenges in controlling the etch profile between metal wire and via structures, leading to depth mismatch issues and damage to underlying structures during the removal of hard masks.

Innovation Solution

The method involves forming an etch stop layer (ESL) on the via layer before creating the metal wire layer, which protects the via structures from etching and allows for the formation of chamferless vias by acting as an etch stop, preventing damage to underlying structures during the metal wire formation process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional dual- or single-damascene processes are used to form interconnect structures, then metal wires and vias can be formed, but the etch profile between metal wire and via structures cannot be controlled, leading to depth mismatch and chamfering of via opening sidewalls

Engineering Contradiction:
Improveetch profile controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

An etch stop layer is formed on the via structure before forming the metal wire structure. This preliminary action prevents the etching process from damaging the via opening sidewalls and enables precise control of the wire opening depth, eliminating chamfering and depth mismatch issues.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etch stop layer acts as an intermediary between the via structure and the wire opening etch process. It protects the via structure from etching while allowing the wire opening to be formed to the precise required depth, solving the etch profile control problem.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If hard mask is used to form via and wire openings, then openings can be defined, but damage is caused to exposed structures underlying the via opening during hard mask removal

Engineering Contradiction:
Improveopening definitionVSAvoiddamage to underlying structures
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The etch stop layer serves as a protective intermediary that prevents damage to underlying structures during hard mask removal. It absorbs the mechanical stress and chemical exposure during the removal process, keeping the via structure intact.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The etch stop layer is placed beforehand to cushion and protect the via structure from damage during subsequent processing steps, particularly during hard mask removal. This protective layer prevents direct exposure of the via structure to damaging processes.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Ease of manufacture

If wire opening depth is not controlled, then via openings can be formed, but the bottom extent of metal wire is not coplanar with via structures, affecting interconnect reliability

Engineering Contradiction:
Improvevia formationVSAvoiddepth alignment
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The etch stop layer is formed preliminarily on the via structure before creating the wire opening. This allows the wire opening etch process to stop precisely at the desired depth, ensuring the bottom extent of the metal wire is coplanar with the via structures, thereby achieving precise depth alignment.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10312188B1Interconnect structure with method of forming the same
Publication Date: 2019.06.04 GLOBALFOUNDRIES US INC
  • US10312188B1 patent drawing
  • US10312188B1 patent drawing
  • US10312188B1 patent drawing

AI summary

An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.