Semiconductor Interconnect Etching With Conductive Etch-Stop Layers
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Solution Overview
Problem
Existing methods for forming interconnect structures in integrated circuits using advanced materials can inadvertently damage underlying dielectric and conductive features during the removal of dielectric hard mask layers, compromising device performance.
Innovation Solution
A method involving the use of a conductive etch-stop layer with enhanced etching selectivity, a hard mask layer resistant to fluorine-containing etchants, and a wet etching process to minimize damage to dielectric layers while patterning conductive lines, ensuring precise and damage-free interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional gases are used to remove dielectric hard mask layer, then the hard mask layer can be removed, but underlying dielectric features and nearby conductive features are inadvertently damaged
Solution Approach 1:
A conductive etch-stop layer is introduced as an intermediary between the hard mask layer and the underlying dielectric/conductive features. This etch-stop layer is selectively removed after the hard mask removal, protecting the underlying features from damage while allowing efficient hard mask removal. The etch-stop layer acts as a buffer that absorbs the harmful effects of the etching process.
Solution Approach 2:
The patent changes the chemical composition parameters of the etchant to achieve selective etching. By using etchants that selectively remove the hard mask layer and subsequent etchants that selectively remove the conductive etch-stop layer, the process enables efficient removal while protecting underlying features. The etching selectivity is achieved through parameter optimization of the etching chemistry.
2Reliability
If advanced materials are introduced for interconnect structures, then device performance is enhanced, but manufacturing complexity and process sensitivity increase
Solution Approach 1:
The fabrication process is segmented into distinct stages with dedicated etch-stop layers for each interconnect level. Each conductive layer is accompanied by its own conductive etch-stop layer, allowing independent optimization and control of each interconnect structure. This segmentation simplifies the overall manufacturing process by breaking down the complex multi-layer fabrication into manageable, repeatable units.
Solution Approach 2:
Conductive etch-stop layers serve as intermediary structures that facilitate the manufacturing of advanced interconnect materials. These etch-stop layers enable selective removal of hard masks and protection of underlying structures, simplifying the fabrication process for advanced materials that would otherwise be difficult to manufacture with conventional processes.
3Object-affected harmful factors
If selective etching is used to protect underlying features, then damage is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The conductive etch-stop layer acts as a mediator that simplifies the etching process by providing a clear, selective target for removal. Rather than attempting to selectively protect multiple underlying features simultaneously, the etch-stop layer provides a single, well-defined layer that can be selectively removed, reducing the precision requirements for the etching process while still protecting underlying features.
Solution Approach 2:
The patent optimizes etching parameters to achieve sufficient selectivity between the conductive etch-stop layer and underlying features. By adjusting etchant composition, temperature, and process conditions, the manufacturing precision requirements are reduced while still achieving the necessary protective effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces unintentional damage to dielectric features and improves the integrity of interconnect structures by providing selective etching and minimizing rounding of conductive line profiles, enhancing the overall performance and reliability of semiconductor devices.
Implementation Method 1
a wet etching process to minimize damage to dielectric layers while patterning conductive lines
Implementation Method 2
conductive etch-stop layer with enhanced etching selectivity
Data Source
AI summary
A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.