Interconnect Structure With Etch Stop Layers for Leakage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing line-to-line leakage and critical dimension (CD) issues due to the limitations of photo-lithographic processes in defining smaller device geometries, which are exacerbated by the increasing density and reduced spacing between components in advanced integrated circuits.
Innovation Solution
The implementation of discrete etch stop layers at different levels and a corner rounding process to form conductive features, along with a dielectric material extending beyond the etch stop layers, reduces the risk of via contact area shrinkage and line-to-line leakage by ensuring precise alignment and dimension control during the manufacturing of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photo-lithographic processes are used to define device geometries, then manufacturing capability is maintained, but manufacturing precision deteriorates due to inability to define smaller dimensions
Solution Approach 1:
The patent segments the manufacturing process into multiple distinct stages: forming mandrels at a first pitch, depositing spacers, selectively removing portions, and forming conductive features at a second, smaller pitch. This segmentation allows each stage to be optimized independently, enabling precise definition of smaller geometries that exceed photo-lithographic capabilities.
Solution Approach 2:
The patent introduces intermediary structures (mandrels and spacers) that serve as templates for forming the final conductive features. These intermediaries are formed at larger dimensions using conventional photo-lithography, then used to define the smaller final geometries through self-aligned processes, effectively bridging the gap between photo-lithographic capabilities and required smaller dimensions.
2Productivity
If device dimensions are reduced to increase density, then productivity improves, but manufacturing precision deteriorates due to new limiting factors
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional self-aligned structures. By forming vertical spacers and multi-layered conductive features, the process achieves smaller effective pitch without requiring proportionally smaller photo-lithographic features, thereby maintaining manufacturing precision while increasing device density.
Solution Approach 2:
The patent performs preliminary actions by forming mandrels and spacers with precise dimensions and positions before forming the final conductive features. These preliminary structures are carefully controlled using conventional photo-lithography and deposition processes, establishing a foundation that enables subsequent self-aligned patterning at smaller dimensions with maintained precision.
3Productivity
If spacing between components is reduced to increase density, then productivity improves, but reliability deteriorates due to line-to-line leakage
Solution Approach 1:
The patent applies local quality by forming discrete etch stop layers at different levels and selectively positioning dielectric materials in specific regions. This creates localized electrical isolation between adjacent conductive features, preventing line-to-line leakage while maintaining reduced spacing between components for increased density.
Solution Approach 2:
The patent segments the dielectric structure into multiple discrete layers and regions, with etch stop layers positioned at different elevations. This segmentation creates multiple isolation barriers between adjacent conductive features, effectively blocking leakage paths while allowing components to be placed closer together for higher density.
4Manufacturing precision
If discrete etch stop layers and corner rounding processes are implemented, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent implements self-aligned processes where previously formed structures (mandrels, spacers) automatically serve as alignment references for subsequent steps. The corner rounding and etch stop layer formation are self-aligned to the spacer structures, eliminating the need for separate alignment operations and reducing the effective complexity increase despite additional process steps.
Data Source
AI summary
An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.