Interconnect Structure With Etch Stop for Via Overlay Reliability
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Solution Overview
Problem
As semiconductor devices transition to nanometer technology process nodes, challenges arise in achieving higher device density and performance while maintaining reliability, particularly in the formation of interconnect structures for FinFETs, where issues like via-to-line overlay, critical dimension control, and time-dependent dielectric breakdown (TDDB) window management are critical.
Innovation Solution
The interconnect structure includes a metal line through a first IMD layer, a dielectric block aligned over a first dielectric layer with an etching stop layer on the dielectric block, a second IMD layer over the etching stop layer, and a via extending through these layers to the metal line, enhancing control over via-to-line overlay, critical dimension, and TDDB windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional interconnect structures are used in nanometer technology nodes, then device density and performance can be increased, but reliability deteriorates due to via-to-line overlay issues, critical dimension control problems, and time-dependent dielectric breakdown
Solution Approach 1:
The interconnect structure is segmented into multiple functional layers: a first dielectric layer, a second dielectric layer, and an etch stop layer positioned between them. This segmentation allows each layer to perform its specific function independently, with the etch stop layer specifically designed to protect the first dielectric layer during via etching processes, thereby preventing TDDB while maintaining the overall interconnect structure's ability to support high device density
Solution Approach 2:
The etch stop layer is formed in advance before via etching occurs. This preliminary action ensures that the protective layer is already in place to prevent damage to the first dielectric layer during subsequent etching operations, addressing reliability concerns before they can manifest during manufacturing processes
2Reliability
If via etching is performed to connect interconnect layers, then electrical connectivity is achieved, but the IMD layer may be damaged leading to time-dependent dielectric breakdown
Solution Approach 1:
The etch stop layer acts as a cushioning protective barrier positioned between the via etch process and the first dielectric layer. This layer absorbs the mechanical and chemical stress of the etching process, preventing direct damage to the IMD layer and eliminating the root cause of time-dependent dielectric breakdown while still allowing via connectivity to be established
3Ease of operation
If traditional multi-layer dielectric structures are used, then interconnect functionality is provided, but capacitance between adjacent lines remains high reducing performance
Solution Approach 1:
The structure implements local quality differentiation by positioning the etch stop layer specifically in regions where via etching occurs, while maintaining different dielectric materials in different spatial zones. This allows optimal capacitance control in high-density interconnect regions while preserving essential interconnect functionality through the layered dielectric structure
Data Source
AI summary
An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.