Interconnect Structure With Discrete Etch Stops for Leakage Control

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Solution Overview

Problem

The reduction in semiconductor device dimensions poses challenges in defining structures photo-lithographically, leading to increased line-to-line leakage and reliability issues.

Innovation Solution

The implementation of discrete etch stop layers at different levels and a corner rounding process to form conductive features, which reduces the risk of via contact area shrinkage and line-to-line leakage by ensuring proper alignment and dimension control of conductive features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor device dimensions are reduced to increase density, then device functionality and performance are improved, but line-to-line leakage increases and manufacturing precision deteriorates

Engineering Contradiction:

Improvedevice densityVSAvoidline-to-line leakage control

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent divides the single etch stop layer into multiple discrete etch stop layers positioned at different vertical levels. This segmentation allows independent control of conductive feature formation at each level, enabling precise dimension control and reduced line-to-line leakage while maintaining high device density

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from controlling conductive features in a single vertical level to multi-level vertical stacking with etch stop layers at different heights. This dimensional approach enables better separation and alignment control of conductive features, reducing lateral leakage while increasing vertical integration density

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If photo-lithographic definition is used for small dimensions, then device geometry is defined, but manufacturing precision and reliability deteriorate due to diffraction and resolution limits

Engineering Contradiction:

Improvestructure definitionVSAvoiddevice reliability

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent performs preliminary patterning and etch stop layer formation before final conductive feature definition. This preliminary action establishes precise vertical references and alignment marks that guide subsequent processing steps, ensuring reliable feature formation at small dimensions where photo-lithography is challenging

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The etch stop layers serve as intermediary structures between the photo-lithographically defined patterns and the final conductive features. These intermediaries provide mechanical and dimensional references that bridge the gap between optical resolution limits and the required precision for small-dimensional reliable feature formation

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12476142B2Semiconductor device structure and methods of forming the same

Publication Date: 2025.11.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.