Semiconductor Interconnect Etching With Metal Etch-Stop Selectivity
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Solution Overview
Problem
Existing methods for fabricating interconnect structures in integrated circuits, particularly when using advanced materials, often inadvertently damage underlying dielectric features and nearby conductive features due to the use of fluorine-containing gases during the etching process, leading to unsatisfactory results.
Innovation Solution
The method involves forming a conductive layer with enhanced etching selectivity using a conductive etch-stop layer and a metal-based hard mask layer, where the conductive layer is susceptible to fluorine-containing gas etching, and the hard mask layer is resistant, allowing for precise patterning of conductive lines while protecting dielectric features. This includes depositing a conductive layer with a distinct composition that is etchable by fluorine-containing gases and a hard mask layer that can be removed using a wet etchant, ensuring minimal damage to the underlying structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fluorine-containing gases are used for etching conductive lines, then etching efficiency is improved, but underlying dielectric features and nearby conductive features are damaged
Solution Approach 1:
The patent segments the etching process into multiple selective etching steps using different gases. First, a chlorine-based gas etches the mandrel material, then a fluorine-based gas etches the conductive line material. This segmentation allows each gas to be optimized for its specific target material without damaging other features.
Solution Approach 2:
The patent applies different etching chemistries to different locations and materials. Chlorine-based etching is used where mandrel material needs removal, while fluorine-based etching is used where conductive line material needs removal. This local differentiation of etching quality prevents cross-damage to dielectric and conductive features.
2Reliability
If advanced materials are introduced in interconnect structures, then device performance is enhanced, but fabrication complexity and process sensitivity increase
Solution Approach 1:
The fabrication process is segmented into distinct patterning and etching steps, each optimized for specific materials. Mandrel formation, selective etching of mandrel material, conductive line formation, and hard mask removal are separated into individual steps with dedicated chemistries, making the complex process more controllable and less sensitive to variations.
Solution Approach 2:
The patent introduces a sacrificial mandrel structure as an intermediary element that facilitates the formation of conductive lines with advanced materials. The mandrel serves as a template that enables precise patterning and protects underlying features during etching, simplifying the overall fabrication of complex interconnect structures.
3Manufacturing precision
If hard mask layer is removed using conventional methods, then pattern transfer is completed, but underlying conductive features and dielectric features are damaged
Solution Approach 1:
The patent changes the chemical parameters of the etching process by using a wet etchant specifically selected to dissolve the hard mask material without attacking conductive or dielectric features. This parameter change enables selective removal of the hard mask while preserving all underlying structures, achieving pattern transfer without damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables direct patterning of conductive lines with improved pattern resolution and reduced damage to dielectric components, maintaining the integrity of the interconnect structures and enhancing the overall performance of the semiconductor device.
Implementation Method 1
the conductive layer is susceptible to fluorine-containing gas etching
Implementation Method 2
the hard mask layer is resistant, allowing for precise patterning of conductive lines while protecting dielectric features. This includes depositing a conductive layer with a distinct composition that is etchable by fluorine-containing gases and a hard mask layer that can be removed using a wet etchant
Data Source
AI summary
A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.