Semiconductor Interconnect Etching for Sub-20 Nm Feature Profiles
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Challenges arise in achieving desired feature profiles for conductive features in semiconductor fabrication as technology nodes continue to evolve toward smaller critical dimensions and pitches, compromising device performance.
Innovation Solution
A method for forming interconnect structures in semiconductor devices involves forming metal lines and via contacts by etching openings in dielectric material layers and filling them with conductive materials, using noble metals for direct patterning and employing etch-stop layers and dielectric capping layers to maintain device performance and precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching and filling processes are used to form conductive features, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at critical dimensions less than 20 nm
Solution Approach 1:
The process is divided into multiple specialized steps: forming etch-stop layers with specific compositions, depositing dielectric capping layers, performing selective etching, and filling conductive materials. Each step addresses a specific requirement for achieving precise sub-20nm critical dimensions, breaking down the complex task into manageable segments with controlled outcomes.
Solution Approach 2:
Different layers are assigned specific local properties: etch-stop layers are positioned at critical interfaces to control etching depth, dielectric capping layers are applied to protect specific regions, and conductive materials are selectively filled. This local differentiation of material properties enables precise control over the final interconnect structure geometry.
2Productivity
If geometry size is scaled down to increase functional density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
Etch-stop layers are formed in advance at predetermined positions within the interconnect structure. These pre-positioned layers serve as reference points that guide subsequent etching processes, ensuring that even as overall dimensions are scaled down, the relative precision of feature formation is maintained through these预先 established reference structures.
Solution Approach 2:
Dielectric capping layers act as intermediary protective elements during the fabrication process. These layers are deposited over specific regions to prevent unwanted material deposition or damage during subsequent processing steps, thereby preserving the intended feature profiles even when working at reduced geometry sizes.
3Manufacturing precision
If etch-stop layers and dielectric capping layers are added to improve manufacturing precision, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The etch-stop layer function is extracted as a separate, dedicated component within the interconnect structure. Rather than attempting to achieve all control functions within the primary dielectric and conductive layers, the etch-stop layer is taken out as a specialized element with the sole purpose of controlling etching depth and position, thereby simplifying the requirements for other layers while improving overall precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures precise formation of interconnect structures with critical dimensions less than 20 nm, maintaining device performance and integrity while accommodating smaller geometry sizes.
Implementation Method 1
perform an etching process to form a first trench in the second interlayer dielectric layer and a second trench in the first interlayer dielectric layer
Implementation Method 2
depositing a conductive layer in the first trench and the second trench, thereby forming a second conductive feature in the second trench and a third conductive feature in the first trench
Data Source
AI summary
A method includes forming a first conductive feature over a substrate, forming an etch-stop layer (ESL) stack over the first conductive feature, forming a first interlayer dielectric (ILD) layer over the ESL stack, forming a patterned ESL having a first opening over the first ILD layer, forming a second ILD layer over the patterned ESL, thereby filling the first opening, forming a patterned HM having a second opening over the second ILD layer, where a width of the second opening is greater than a width of the first opening, performing an etching process to form a first trench in the second ILD layer and a second trench in the first ILD layer, where the second trench exposes the first conductive feature, and subsequently depositing a conductive layer in the first trench and the second trench, thereby forming a second conductive feature interconnecting a third conductive to the first conductive feature.