Interconnect Fabric Cache Steering for I/O Writes
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Solution Overview
Problem
Conventional processing systems require at least two high-latency memory access operations for I/O devices to make data available to processing cores, which limits memory subsystem availability and efficiency due to dual data rate memory architectures that cannot perform concurrent read and write operations.
Innovation Solution
Implementing steered I/O write operations where data is buffered at an interconnect fabric and directed to a target cache, eliminating the need for direct memory access from system memory by using techniques such as software steering indicators, coherency information, or pre-configured hardware initialization to identify and instruct the target cache to prefetch the data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DMA read operations are used to transfer I/O data to system memory, then data can be accessed by processing cores, but at least two high-latency memory access operations are required before data is available for use
Solution Approach 1:
The patent steers I/O write operations to prefetch data directly into the cache hierarchy of compute complexes before the processing cores need the data. By performing the data transfer in advance and directing it to the appropriate cache (L2 or L3), the system eliminates the need for subsequent high-latency memory access operations when the processing core needs the data.
Solution Approach 2:
The patent introduces an interconnect fabric with steering capability that acts as an intermediary between I/O devices and the memory hierarchy. This fabric can intercept I/O write operations and redirect them to specific compute complex caches rather than allowing them to proceed to system memory, thereby reducing the number of memory access operations required.
2Productivity
If dual data rate memory architecture is used to allow concurrent read and write operations, then memory bandwidth is improved, but the memory bus is limited to either read or write at any given time
Solution Approach 1:
The interconnect fabric serves as a mediator that captures I/O write operations before they reach the memory controller. By steering these operations to compute complex caches, the fabric prevents memory bus conflicts between concurrent read and write operations, thereby improving memory subsystem availability without requiring complex memory bus arbitration.
3Reliability
If I/O data is written to system memory first and then accessed by processing cores, then data can be cached at compute complex, but the sequential memory access operations impact memory subsystem availability for other requesters
Solution Approach 1:
The interconnect fabric acts as an intermediary that redirects I/O write operations directly to compute complex caches, bypassing system memory for these operations. This eliminates the sequential access pattern that impacts memory subsystem availability, while still ensuring reliable data transfer to the processing cores through the cache hierarchy.
Solution Approach 2:
The patent segments the memory hierarchy into distinct paths: I/O write operations are steered to compute complex caches (L2/L3) while system memory remains available for other requesters. This segmentation allows concurrent operations without conflict, improving overall memory subsystem availability while maintaining data transfer reliability.
Data Source
AI summary
A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.