Interconnect Fabric Placement for Congestion and Timing Closure
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Solution Overview
Problem
The physical design of System-on-a-Chip (SoC) interconnect fabrics is challenging due to congestion overflow and non-uniform placement of components, leading to inefficient design cycles, increased power consumption, and delayed development timelines.
Innovation Solution
A congestion-aware placement method for interconnect fabric components using a virtual grid to optimize placement and minimize Total Wirelength (TWL) cost functions, followed by inserting timing slices based on port distances, reducing the need for iterative design iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional placement methods are used for interconnect fabric components, then the design process is simpler, but congestion overflow occurs and routing efficiency deteriorates
Solution Approach 1:
The patent applies preliminary action by performing congestion-aware placement of fabric components before the actual routing process. The placement optimizer uses a cost function that predicts routing congestion based on component locations, allowing the system to proactively position components to minimize future routing issues rather than reacting to congestion problems after routing begins. This preliminary optimization of component placement based on predicted congestion patterns resolves the contradiction by improving routing efficiency through advance planning without requiring complex real-time routing adjustments.
2Manufacturing precision
If iterative design cycles are used to resolve congestion, then placement accuracy improves, but development time increases
Solution Approach 1:
The patent implements self-service through an automated placement optimization system that independently adjusts fabric component locations based on congestion predictions. The optimizer automatically evaluates different placement configurations using a cost function and selects the optimal arrangement without requiring manual intervention or multiple iterative design cycles. This self-service approach achieves high placement precision in a single pass, eliminating the time-consuming iterative process while maintaining manufacturing precision through algorithmic optimization.
3Reliability
If more timing slices are inserted to meet timing requirements, then timing closure is achieved, but power consumption and cell count increase
Solution Approach 1:
The patent applies preliminary action by optimizing fabric component placement before timing analysis to minimize the number of timing slices required. The cost function evaluates placement configurations based on their impact on timing paths, allowing the system to pre-position components in locations that naturally satisfy timing requirements with fewer slices. This preliminary optimization reduces the need for additional timing slices, thereby lowering power consumption and cell count while achieving timing closure.
Data Source
AI summary
Techniques are provided for congestion aware placement of the fabric components of an interconnect in an integrated circuit device. A floorplan of the interconnect is projected on a virtual grid that includes placement locations for the fabric components. Locations of the fabric components can be initialized with the placement locations of the virtual grid. Updated locations for the placement of each of the fabric components on the virtual grid can be determined based on minimization of a total wirelength (TWL) cost function of all the nets in the interconnect. Timing slices are inserted in the interconnect after the placement of the fabric components at the updated locations. The floorplan information with the placement information of the fabric components and the timing slices can be used for the physical design of the interconnect to provide a timing clean result.