Interconnect Fabric Routing Protocol with Priority Arbiter

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Solution Overview

Problem

Current parallel processing technologies face challenges in scalable, cost-effective, and energy-efficient data communication among multiple processors, with bus-based interconnects being non-scalable and performance issues with flow control techniques leading to latency problems.

Innovation Solution

A flit-buffer flow control protocol with a default interrupt mode and transient switching mode, utilizing an arbiter and interleave mechanism with CRC encoding to enable seamless data transfer and low latency, particularly in a 'wormhole' switching mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If bus-based interconnect is used for processor communication, then communication capability is provided, but scalability is limited and cost increases

Engineering Contradiction:
ImprovescalabilityVSAvoidinterconnect complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the interconnect fabric into multiple independent routing domains and switches, replacing the monolithic bus-based interconnect. Each switch handles local routing independently, enabling the system to scale by adding more switches and processors without increasing overall system complexity proportionally.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a one-dimensional bus topology to a multi-dimensional mesh or fabric topology with multiple routing paths. This dimensional change allows data to travel through alternative routes, improving scalability and reducing contention as the system grows.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If flow control techniques are used for data routing, then data transfer is enabled, but latency increases due to control overhead

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidcontrol latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements flow control credits and routing information in advance, allowing data flits to be transmitted without waiting for real-time buffer availability checks. The receiver pre-allocates buffer space and sends credit information back, enabling the transmitter to send data continuously without stalling, thus reducing latency while maintaining flow control.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous data transmission through credit-based flow control and virtual channel mechanisms. Instead of stopping transmission for buffer management, the system maintains continuous useful action by using pre-negotiated credits and multiple virtual channels that can be switched between without interrupting the data flow.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11516143B2Routing and control protocol for high-performance interconnect fabrics
Publication Date: 2022.11.29 LIGHTFLEET CORP
  • US11516143B2 patent drawing
  • US11516143B2 patent drawing
  • US11516143B2 patent drawing

AI summary

Operating a computer network uses a routing and control protocol, the computer network having an interconnect fabric including routing and control distribution devices and fabric interface devices, each of the routing and control distribution devices and each of the fabric interface devices having a state machine having an input processing unit having parallel input buffers, an output processing unit having parallel output buffers and an arbiter; operating the state machine based on a set of instructions and a table located at the state machine; transferring data from the input processing unit to the output processing unit; choosing a highest priority currently flit occupied parallel input buffer located in the input processing unit for data transmission on a highest priority currently flit occupied channel; and; interrupting the highest currently flit occupied priority channel when one of the parallel input buffers is detected to contain a superseding even higher priority flit.