High-Speed Interconnect FEC for Compressed Symbol Streams

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Solution Overview

Problem

High-speed serial interconnects, such as DisplayPort, face challenges in error correction, especially for compressed symbol streams, where random bit errors can corrupt entire frames, leading to unacceptable data loss.

Innovation Solution

The implementation of forward error correction (FEC) techniques using Reed-Solomon encoding and symbol interleaving to add redundancy to the symbol stream, enabling detection and correction of bit errors, particularly for DisplayPort standards like v1.3 and v1.4, which split the symbol stream into FEC blocks and generate parity bytes to correct errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If forward error correction (FEC) techniques are implemented to correct bit errors in compressed symbol streams, then data reliability is improved, but device complexity increases

Engineering Contradiction:

Improvedata transmission reliabilityVSAvoiderror correction system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The symbol stream is divided into multiple symbol blocks, where each block contains a specific number of symbols (e.g., 256 symbols per block). FEC parity symbols are calculated for each block independently, allowing localized error correction without processing the entire stream at once. This segmentation reduces computational complexity while maintaining reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

FEC parity symbols are pre-calculated and inserted into the symbol stream before transmission. The transmitter performs the encoding operation in advance, so that the receiver only needs to perform simpler decoding and error correction operations. This preliminary action shifts computational burden to the transmitter and simplifies the receiver design.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If FEC parity symbols are inserted into the symbol stream, then error correction capability is improved, but bandwidth utilization decreases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidbandwidth utilization

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

Instead of adding FEC redundancy to the entire symbol stream uniformly, the patent applies FEC locally to specific symbol blocks. Each block receives FEC protection independently, allowing the system to provide error correction capability where needed while minimizing the overall overhead. The local application of FEC ensures that only necessary portions of the data consume additional bandwidth for redundancy.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11990996B2High speed interconnect symbol stream forward error-correction

Publication Date: 2024.05.21 INTEL CORP

AI summary

Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.