Semiconductor Interconnect Filling Layer With Sealed Air Gap
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly due to issues with parasitic capacitance between conductive layers.
Innovation Solution
A semiconductor device design incorporating a filling layer made of boron carbonitride with an air gap, which reduces parasitic capacitance by employing a low dielectric constant material and an air gap sealed by a dielectric layer, thereby enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional filling materials are used between conductive layers, then the structure is simple and easy to manufacture, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
The filling layer is formed as a composite structure comprising a first filling material layer and a second filling material layer with different dielectric constants. The first layer has a higher dielectric constant than the second layer, creating a gradient structure that reduces parasitic capacitance between conductive layers while maintaining manufacturing feasibility through sequential deposition processes
Solution Approach 2:
Different regions of the filling layer are assigned different dielectric properties - the first filling material layer closer to the conductive layers has higher dielectric constant for better field control, while the second layer has lower dielectric constant to reduce parasitic capacitance. This local differentiation optimizes electrical performance without requiring complete structural redesign
2Reliability
If dielectric layers are added to reduce parasitic capacitance, then device performance improves, but manufacturing complexity and process steps increase
Solution Approach 1:
The filling layer structure combines multiple dielectric materials in a vertically stacked configuration between conductive layers, merging the functions of field control and capacitance reduction into a single integrated layer system. This approach achieves parasitic capacitance reduction without requiring separate additional dielectric layers, thereby limiting the increase in manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a boron carbonitride filling layer with an air gap effectively reduces parasitic capacitance between conductive layers, leading to improved semiconductor device performance.
Implementation Method 1
the parasitic capacitance between the plurality of conductive layers may be reduced by employing the filling layer having low dielectric constant and the air gap
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of conductive layers positioned on the substrate; a filling layer positioned between the plurality of conductive layers; an air gap positioned in the filling layer; and a dielectric layer positioned on the plurality of conductive layers and the filling layer. The filling layer includes boron carbonitride.