Interconnect Flatness via Convex Dielectric Pre-Shaping
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Solution Overview
Problem
The dual damascene process in semiconductor manufacturing often results in dishing defects due to the discontinuity in mechanical properties between metal and insulator layers, leading to poor flatness of conductor surfaces and increased pressure requirements for bonding, which reduces device yield and introduces additional costs and defects.
Innovation Solution
A method involving the deposition of a conductive sacrificial layer with a lower corrosion or polishing rate than the conductor, followed by chemical mechanical polishing to create a convex or flat surface within the interconnect structures, ensuring the conductor surface is angled greater than or equal to zero with respect to the substrate, thereby eliminating dishing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual damascene process is used to form interconnect structures, then device density and yield are improved, but dishing defects occur due to discontinuity in mechanical properties between metal and insulator layers
Solution Approach 1:
A convex structure is formed in the dielectric layer prior to depositing the conductor material. This preliminary shaping of the dielectric surface compensates for the expected dishing that will occur during subsequent CMP processing, ensuring the final conductor surface achieves the desired flatness after polishing
Solution Approach 2:
The mechanical properties and surface topology of the dielectric layer are modified by forming a convex structure with specific geometry (height, width, positioning). This parameter change in the dielectric layer's surface profile directly counteracts the dishing effect, transforming the surface topology to achieve flatness in the final conductor layer
2Manufacturing precision
If conventional CMP polishing is applied to interconnect structures, then metal cavities are planarized, but erosion occurs in high metal pattern density features and dishing in large metal structures
Solution Approach 1:
A convex structure is preliminarily formed in the dielectric layer to counteract the expected dishing effect. This pre-positioned convexity acts as a compensatory feature that prevents the harmful dishing defect from developing in the final conductor surface, effectively anticipating and neutralizing the polishing-induced deformation
Solution Approach 2:
The dielectric layer is pre-shaped with a convex structure before conductor deposition and CMP processing. This preliminary structural modification creates a surface profile that compensates for the non-uniform material removal during polishing, preventing erosion in high-density areas and dishing in large structures
3Stress or pressure
If poor flatness of conductor surface is accepted, then bonding pressure requirements increase, but device yield decreases and additional costs are incurred
Solution Approach 1:
A convex structure is formed in the dielectric layer before bonding operations to pre-compensate for surface flatness issues. This preliminary structural adjustment ensures that the conductor surface achieves adequate flatness, thereby reducing the bonding pressure required and preventing yield loss from poor bonding quality
Solution Approach 2:
The surface topology parameters of the dielectric layer are modified by forming a convex structure with specific dimensional parameters. This parameter change directly influences the final conductor surface flatness, enabling bonding at lower pressures and improving device yield by eliminating bonding defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces dishing defects, improves the flatness of conductor surfaces, and simplifies the bonding process, enhancing device yield and reducing costs by eliminating the need for selective recessing of dielectric layers.
Implementation Method 1
chemical mechanical polishing to create a convex or flat surface within the interconnect structures
Data Source
AI summary
In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, “first” layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.