Interconnect Link Layer Flit Layout for Scalable Coherent Bandwidth
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in scaling bandwidth and efficiency as the number of processing units and devices increases, leading to complexity and power consumption issues, particularly in balancing performance and power usage across different market segments.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that employs a next-generation, cache-coherent, link-based interconnect with a layered protocol stack, including a routing layer, link layer, and physical layer, along with features like power management, fault handling, and virtual channel services, to enhance data transfer and management between processors and I/O devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional multi-drop buses are used for interconnect, then electrical communication is simplified, but bandwidth and communication speed deteriorate
Solution Approach 1:
The patent segments the interconnect architecture from traditional multi-drop buses into point-to-point links with separate transmit and receive paths. Each processor socket gets dedicated communication channels, dividing the shared bus into multiple independent links that can operate simultaneously, thereby increasing overall communication speed while maintaining manageable complexity through modular design
Solution Approach 2:
The patent transitions from a single-dimensional shared bus architecture to a multi-dimensional point-to-point link structure with separate transmit and receive dimensions. This allows full-duplex communication where data can flow in both directions simultaneously across the same physical medium, effectively doubling the communication capacity without proportionally increasing complexity
2Power
If the number of processing units increases, then computing power increases, but interconnect bandwidth requirements worsen
Solution Approach 1:
The patent creates a universal point-to-point link architecture that can accommodate any number of processing units through standardized interfaces. Each link is designed to be multi-functional, handling different types of traffic (memory access, I/O operations, processor communication) simultaneously, allowing the interconnect to scale with computing power without requiring proportional increases in dedicated bandwidth for each function
Solution Approach 2:
The patent implements dynamic resource allocation in the interconnect where bandwidth is not statically assigned but dynamically adjusted based on actual communication needs. The protocol layer can prioritize different types of traffic and allocate link capacity dynamically, allowing the system to handle varying workloads efficiently as computing power scales, preventing bandwidth from becoming a bottleneck
3Area of moving object
If more devices are integrated in smaller packages, then device density improves, but communication between sockets deteriorates
Solution Approach 1:
The patent introduces a protocol layer as an intermediary between the physical proximity of devices and the communication reliability requirement. This protocol layer handles error detection, correction, and retransmission, acting as a mediator that ensures reliable communication even when devices are densely packed and subject to increased interference and signal degradation from close proximity
Data Source
AI summary
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.