Interconnect Link Layer Flit Format for Bandwidth and Power Control
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in scaling bandwidth and efficiency as the demand for faster communication between processors and devices increases, particularly in servers and mobile ecosystems, where power consumption and performance trade-offs are critical.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that employs a next-generation, cache-coherent, link-based interconnect with a layered protocol stack, including a routing layer, link layer, and physical layer, which supports multiple devices and configurations, and incorporates features like credit-based flow control, virtual channels, and flexible routing to optimize data transfer and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but communication speed and bandwidth are limited
Solution Approach 1:
The patent segments the interconnect architecture into multiple independent point-to-point links instead of using a shared multi-drop bus. Each link operates independently with dedicated resources, enabling simultaneous communications between multiple device pairs. This segmentation resolves the contradiction by providing high-speed dedicated paths while maintaining manageable individual link complexity.
Solution Approach 2:
The patent transitions from a one-dimensional shared bus architecture to a multi-dimensional mesh-like topology where devices can communicate directly along multiple independent paths. This dimensional change enables parallel communications and significantly increases overall system bandwidth without proportionally increasing individual link complexity.
2Productivity
If more processing power is added to integrated circuits, then computing performance increases, but communication demand between devices increases
Solution Approach 1:
The patent implements credit-based flow control where receiving devices pre-allocate buffer credits to transmitting devices before data transfer begins. This preliminary action prevents data stalls and reduces the need for retransmissions and flow control wait states, thereby lowering communication energy consumption while supporting high-performance computing workloads.
Solution Approach 2:
The patent ensures continuous data flow through mechanisms like out-of-order delivery and completion, allowing transmitting devices to maintain high utilization without idle wait states. This continuity eliminates gaps in useful communication action, reducing overall energy consumption per unit of data transferred while maintaining high computing performance.
3Productivity
If higher data transfer rates are demanded, then performance requirements are met, but power consumption increases
Solution Approach 1:
The patent implements dynamic link power management where interconnect links can be dynamically activated or deactivated based on actual communication demand. Links that are not currently in use can be powered down or placed in low-power states, while active links operate at high data transfer rates. This dynamic approach resolves the contradiction by providing high performance when needed while minimizing power consumption during idle periods.
Data Source
AI summary
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.