Multi-chip Package Interconnect Frame for Thermal and Signal Management
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Solution Overview
Problem
The miniaturization of 2.5/3D semiconductor packaging leads to increased package z-height and real-estate challenges, signal line congestion, electrical performance impairments such as signal latency and attenuation losses, and heat dissipation issues due to the crowded package environment, particularly in high-data-rate applications.
Innovation Solution
A multi-chip semiconductor package design featuring an interconnect frame with an extended redistribution layer, recessed areas for chip placement, and embedded passive devices or thermal spreaders to reduce package footprint, enhance interconnect bandwidth, and improve thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If package miniaturization is implemented to reduce footprint, then area of package substrate is reduced, but package z-height increases and heat dissipation becomes more difficult
Solution Approach 1:
The patent extends the interconnect frame beyond the package substrate edges into the packaging void space, utilizing three-dimensional space rather than being constrained to the two-dimensional substrate plane. This dimensional transition allows interconnects to route outside the substrate footprint, reducing congestion and improving thermal characteristics while maintaining a compact substrate footprint.
2Area of stationary object
If package footprint is reduced for miniaturization, then area of package substrate is reduced, but signal line routing congestion increases
Solution Approach 1:
The interconnect frame extends beyond the substrate edges into the packaging void, enabling signal lines to route in the third dimension outside the congested substrate area. This provides additional routing space and reduces signal line congestion while maintaining a compact substrate footprint.
Solution Approach 2:
The extended interconnect frame acts as an intermediary structure that bridges the substrate and external packaging space. It provides a dedicated routing pathway for signal lines, separating them from the crowded substrate environment and reducing routing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves reduced package substrate real-estate, improved electrical performance through higher bandwidth density and reduced signal latency, and enhanced thermal dissipation, addressing the challenges of miniaturization and heat management in high-data-rate applications.
Implementation Method 1
embedded passive devices or thermal spreaders to reduce package footprint, enhance interconnect bandwidth, and improve thermal dissipation
Data Source
AI summary
According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.