Interconnect Gap Structure for Lower Capacitance in Semiconductor Wiring

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Solution Overview

Problem

Existing semiconductor technologies face challenges in reducing inter-wiring capacitance, particularly as wiring lines become finer, leading to increased wire delay due to higher wiring resistance and capacitance, which is exacerbated by the difficulty in forming gaps between wiring lines with varying distances.

Innovation Solution

A semiconductor device and manufacturing method that involve a first inter-wiring insulating layer with a recess, a first wiring layer embedded within, a sealing film along the uneven shape, and a second inter-wiring insulating layer with a planarized surface, allowing for the formation of a gap between the second inter-wiring insulating layer and the first wiring and insulating layers, thereby reducing inter-wiring capacitance regardless of the wiring layout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If non-conformal deposition film formation such as CVD is used to place deposits above the wiring lines before the space between the wiring lines is filled with a deposit, then a gap can be formed between wiring lines, but it becomes more difficult to form a gap as the wiring lines have a longer distance

Engineering Contradiction:
Improvegap formation between wiring linesVSAvoiddifficulty in forming gap for long-distance wiring lines
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent divides the gap formation process into two distinct stages: first forming a preliminary gap structure using non-conformal deposition, then completing the gap formation by filling the space between wiring lines with additional deposit. This segmentation allows the process to handle both short and long distance wiring lines effectively, as each stage addresses specific requirements that the other cannot satisfy alone.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary gap formation by placing deposits above the wiring lines using non-conformal deposition before filling the space between wiring lines. This preliminary action creates a foundation structure that facilitates subsequent complete gap formation, particularly for wiring lines with varying distances, by pre-establishing the gap geometry in areas where it is most needed.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the space between the wiring lines is filled with a deposit, then a gap can be formed between wiring lines, but the inter-wiring capacitance cannot be reduced for wiring lines with varying distances

Engineering Contradiction:
Improvegap formation consistencyVSAvoidapplicability to any wiring layout
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal gap formation method that can be applied to any wiring layout regardless of line distance by combining non-conformal deposition with subsequent space filling. The non-conformal deposition step universally places deposits above all wiring lines, and the subsequent filling step universally completes the gap formation, making the process adaptable to short-distance, long-distance, and mixed-distance wiring configurations alike.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent applies different deposition characteristics to different regions: non-conformal deposition places thicker deposits above wiring lines where gaps are needed, while the subsequent filling step uniformly fills the spaces between lines. This local quality approach ensures consistent gap formation whether the wiring lines are close together or far apart, as each region receives the appropriate amount of material.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11901392B2Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2024.02.13 SONY SEMICON SOLUTIONS CORP
  • US11901392B2 patent drawing
  • US11901392B2 patent drawing
  • US11901392B2 patent drawing

AI summary

There is provided a semiconductor device in which the inter-wiring capacitance of wiring lines provided in any layout is further reduced. A semiconductor device that includes a first inter-wiring insulating layer that is provided on a substrate and includes a recess on a side opposite to the substrate, a first wiring layer that is provided inside the recess in the first inter-wiring insulating layer, a sealing film that is provided along an uneven shape of the first wiring layer and the first inter-wiring insulating layer, a second inter-wiring insulating layer that is provided on the first inter-wiring insulating layer to cover the recess, and a gap that is provided between the second inter-wiring insulating layer and the first wiring layer and the first inter-wiring insulating layer. The second inter-wiring insulating layer has a planarized surface that is opposed to the recess.