Interconnect Grain Growth Promotion Layer for Copper Microstructure Control
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Solution Overview
Problem
In interconnect structures, the grain growth rate of copper (Cu) is faster in the plated layer than in the seeding layer, leading to small grains at the bottom of features, which is a challenge as interconnect structures shrink, necessitating an improved method for maintaining optimal Cu microstructure.
Innovation Solution
A method involving the formation of a diffusion barrier layer, a Cu seeding layer, and a grain growth promotion layer, followed by post-processing steps like electroplating and chemical-mechanical polishing, to enhance grain growth and microstructure in interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Cu plating is performed directly on top of a Cu seeding layer followed by high temperature annealing, then the process is simple, but the grain growth rate is faster in the plated Cu than in the seeding layer, resulting in small grains at the bottom of interconnect features
Solution Approach 1:
A grain growth promotion layer composed of Ru, Ir, Rh, Mo, Re, Hf, Nb, Pt, or their alloys is introduced between the Cu seeding layer and the plated Cu layer. This intermediary layer acts as a catalyst during annealing to promote uniform grain growth throughout the interconnect structure, preventing the formation of small grains at the bottom while maintaining process feasibility.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers with different materials: a diffusion barrier layer, a Cu seeding layer, a grain growth promotion layer, and a plated Cu layer. Each layer serves a specific function, and their combination achieves both uniform grain growth and processability.
2Volume of moving object
If interconnect structures are continually shrunk to achieve higher density, then the integration density improves, but the grain growth rate becomes insufficient to maintain optimal Cu microstructure
Solution Approach 1:
The patent changes the chemical composition parameter by introducing a grain growth promotion layer with specific materials (Ru, Ir, Rh, Mo, Re, Hf, Nb, Pt or their alloys) that have different catalytic properties. This parameter change enables controlled grain growth even in miniaturized interconnect structures where traditional annealing is insufficient.
Solution Approach 2:
The grain growth promotion layer serves as a mediator that facilitates atomic diffusion and grain boundary movement during annealing. This intermediary enables reliable Cu microstructure formation in scaled-down interconnect features by providing a controlled mechanism for grain growth that is independent of the absolute feature size.
3Manufacturing precision
If a grain growth promotion layer is added to improve grain growth, then larger Cu grain sizes are achieved, but the process complexity increases
Solution Approach 1:
The grain growth promotion layer is applied locally only where needed - specifically on top of the Cu seeding layer in the interconnect features. This localized approach provides the necessary grain growth control precisely where it is needed without unnecessarily complicating the entire device structure.
Solution Approach 2:
The grain growth promotion layer is nested within the existing interconnect stack, fitting between the diffusion barrier layer and the plated Cu layer. This nested structure integrates the new functionality within the existing architecture rather than adding external complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved circuit performance and reliability by promoting larger Cu grain sizes, reducing wire resistance and increasing time to fail, as depicted in the provided graphs.
Implementation Method 1
a grain growth promotion layer (e.g., Ru, Ir, Rh, Mo, Re, Hf, Nb, Pt, and/or related alloy materials) is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.
Implementation Method 2
a grain growth promotion layer (e.g., Ru, Ir, Rh, Mo, Re, Hf, Nb, Pt, and/or related alloy materials) is formed on the seeding layer
Implementation Method 3
a diffusion barrier layer (e.g., Ta, Ti, Ru, W, and/or related nitride materials) is formed on a patterned inter-level dielectric layer
Implementation Method 4
post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed
Implementation Method 5
post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed
Data Source
AI summary
In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed.