Interconnect Grating Replication for Self-Aligned Via Patterning
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Solution Overview
Problem
Current semiconductor technologies lack flexibility in accommodating interconnect designs with multiple pitches and varying feature widths, limiting the ability to form self-aligned vias and conductive traces with precise alignment.
Innovation Solution
The use of topographically-selective deposition processes, specifically atomic layer deposition (ALD), to replicate gratings in subsequent layers, allowing for the formation of conductive traces with multiple pitches and widths, and the use of helmet layers as masks to transfer grating patterns, ensuring precise alignment of vias and conductive traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to form vias, then overlay errors occur leading to misalignment, but self-aligned technologies have limitations in pitch and feature width flexibility
Solution Approach 1:
The patent uses grating replication to copy the pattern from a first interconnect layer to a second interconnect layer. A grating structure is formed in the first layer, then a helmet layer is deposited and patterned to replicate this grating pattern in the second layer, ensuring precise alignment without overlay errors while maintaining flexibility in pitch and feature width
Solution Approach 2:
The patent introduces a vertical dimension by forming a helmet layer that extends above the interconnect layers. This helmet layer serves as a three-dimensional mask that replicates the grating pattern, allowing precise alignment to be achieved through vertical stacking rather than relying solely on planar lithographic alignment
2Reliability
If design rules require larger via distances from conductive trace edges to prevent shorting, then manufacturing reliability improves, but device density decreases
Solution Approach 1:
The patent employs self-aligned patterning where the helmet layer automatically positions itself relative to the underlying grating structure. This self-alignment mechanism ensures that vias are precisely positioned without requiring conservative design rules, allowing conductive traces to be placed closer together while maintaining reliability and preventing shorting
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of self-aligned interconnect structures with improved precision and flexibility, reducing overlay errors and enhancing the density and reliability of semiconductor devices.
Implementation Method 1
selectively depositing a helmet layer over the first conductive traces, wherein the helmet layer is deposited with an atomic layer deposition (ALD) processes that comprises spinning a substrate on which the interconnect structure is formed
Data Source
AI summary
Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.