Interconnect Hazard Management for Ordered Write Observation

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Solution Overview

Problem

Interconnects face challenges in maintaining Ordered Write Observation (OWO) behavior while reducing latency and complexity, as deadlock avoidance circuitry increases latency and is costly, and existing solutions struggle to efficiently manage OWO behavior without relying on complex deadlock avoidance schemes.

Innovation Solution

The interconnect employs hazard management circuitry to serialize transactions and gating circuitry to ensure OWO behavior, allowing the hazard management circuitry to control the gating operation, thereby reducing the need for deadlock avoidance circuitry and minimizing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If deadlock avoidance circuitry is used to ensure OWO behavior, then reliability is improved, but latency increases and device complexity increases

Engineering Contradiction:
ImproveOWO behaviorVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines the OWO enforcement function with the existing hazard management circuitry by integrating a gate controller into the hazard management unit. The gate controller uses the same hazard information (transactions to overlapping addresses) already being tracked by the hazard management circuitry to control write transaction propagation, eliminating the need for separate deadlock avoidance circuitry to enforce OWO behavior.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hazard management circuitry is enhanced to perform multiple functions: it continues to serialize transactions to overlapping addresses for hazard prevention while simultaneously enforcing OWO behavior through the integrated gate controller. This multi-functional approach allows a single circuit to address both hazard management and OWO requirements without adding separate dedicated circuitry.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If deadlock avoidance circuitry is used to ensure OWO behavior, then reliability is improved, but device complexity increases

Engineering Contradiction:
ImproveOWO behaviorVSAvoidinterconnect complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the OWO enforcement functionality into the existing hazard management circuitry structure. The gate controller is integrated within the hazard management unit and utilizes the same hazard transaction information already being tracked, thereby avoiding the addition of separate complex deadlock avoidance circuits while still ensuring OWO behavior.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hazard management circuitry enhances its own functionality by incorporating the gate controller that uses its internally tracked hazard information to enforce OWO behavior. The circuitry serves itself by using its existing hazard tracking data to control write transaction propagation, eliminating the need for external deadlock avoidance circuitry.

Inventive Principle:
Principle #25Self-service

3Speed

If write response re-order buffers are used to reduce latency, then speed is improved, but device complexity increases and OWO behavior must still be ensured

Engineering Contradiction:
Improvewrite transaction speedVSAvoidinterconnect complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts the OWO enforcement function from the write response re-order buffer path and places it in the hazard management circuitry. By enforcing OWO behavior at the write transaction issuance stage through hazard-based gating, the system eliminates the need for complex re-order buffering mechanisms to manage OWO, thereby reducing overall device complexity while maintaining speed improvements.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The gate controller performs preliminary action by preventing write transactions from being issued to the interconnect until OWO safety conditions are met, based on hazard information from overlapping address transactions. This proactive enforcement at the source eliminates the need for corrective re-ordering mechanisms downstream, reducing complexity compared to using write response re-order buffers.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9928195B2Interconnect and method of operation of an interconnect for ordered write observation (OWO)
Publication Date: 2018.03.27 ARM LTD
  • US9928195B2 patent drawing
  • US9928195B2 patent drawing
  • US9928195B2 patent drawing

AI summary

An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.