Interconnect Header Filaments for Through-Silicon Die Coupling
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Solution Overview
Problem
The manufacturing of through-silicon vias (TSVs) is challenging due to process variations and cost constraints, and conventional interconnect methods like wire bonds increase labor and costs while lengthening interconnect distances.
Innovation Solution
An electronic assembly system with a primary die featuring a bulk layer through-hole and integrated circuitry through-hole, electrically coupled via an interconnect header comprising conductive filaments, which can be generated using standard semiconductor foundry methods, reducing complexity and cost compared to TSVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to establish interconnects through the bulk silicon side, then electrical coupling between metal layers and attachment layers is achieved, but manufacturing complexity and cost increase due to process variations
Solution Approach 1:
The through-silicon via structure is segmented into multiple components: bulk layer through-holes, integrated circuitry through-holes, metal layer through-holes, and an interconnect header with conductive filaments. This segmentation allows each component to be manufactured using standard, well-controlled processes rather than requiring complex TSV formation, thereby reducing manufacturing complexity while maintaining electrical coupling reliability
Solution Approach 2:
An interconnect header containing conductive filaments is introduced as an intermediary component between the through-holes and the metal/attachment layers. This intermediary simplifies the electrical coupling process by providing a standardized interface that can be manufactured using conventional semiconductor fabrication techniques, avoiding the complexity of direct TSV formation
2Ease of manufacture
If wire bonds or perimeter located vertical interconnects are used, then interconnects can be implemented, but interconnect distances are lengthened and labor and costs increase
Solution Approach 1:
The interconnect path is moved from the perimeter dimension to the bulk dimension by creating through-holes through the bulk silicon layer. This dimensional change allows direct vertical electrical coupling between front-side metal layers and back-side attachment layers, significantly reducing interconnect distance compared to perimeter-based wire bonds while maintaining ease of manufacture through standard through-hole fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides efficient and cost-effective through-die connections, similar to TSVs but with simpler and less expensive methods, reducing manufacturing time and labor while maintaining effective electrical coupling between dies.
Implementation Method 1
an interconnect header that includes a plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer
Data Source
AI summary
An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.