Interconnect Logic ID Aliasing for Deadlock Avoidance
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Solution Overview
Problem
Cyclic dependency deadlocks occur in data processing apparatuses using split transaction protocols due to the ability of slave logic units to reorder transactions with different transaction identifiers, leading to performance issues and potential system crashes, which existing deadlock avoidance schemes address by constraining master logic unit behavior or using complex prediction logic.
Innovation Solution
Implementing ID aliasing logic in the interconnect logic, where slave logic units can replace transaction identifiers with a predetermined identifier for specific transactions, ensuring these transactions are processed in order and preventing reordering between them, thus avoiding deadlocks without constraining master logic unit behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If slave logic units reorder transactions with different transaction identifiers to improve performance, then transaction processing efficiency is improved, but cyclic dependency deadlocks occur leading to system crashes
Solution Approach 1:
The patent introduces interconnect logic as an intermediary component between master logic units and slave logic units. This intermediary monitors transaction identifiers and controls the reordering process, allowing slave logic units to reorder transactions only when it is safe to do so, thereby preventing deadlocks while maintaining performance improvements
Solution Approach 2:
The interconnect logic implements feedback mechanisms by tracking transaction identifiers and their processing states. It provides feedback control over the reordering operation, enabling slave logic units to dynamically adjust their reordering behavior based on system state, thus preventing cyclic dependency deadlocks
2Reliability
If complex prediction logic is used to avoid deadlocks, then system reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the deadlock avoidance functionality from complex prediction logic and implements it through simpler interconnect logic that monitors transaction identifiers. This separation allows slave logic units to maintain reordering capability while the interconnect logic handles the complexity of deadlock prevention through straightforward identifier tracking
Solution Approach 2:
The patent changes the approach from complex behavioral prediction to simple parameter monitoring. By tracking transaction identifiers as key parameters, the interconnect logic can determine safety of reordering using straightforward parameter comparison rather than complex prediction algorithms, reducing device complexity
3Reliability
If master logic unit behavior is constrained to avoid deadlocks, then system reliability is improved, but ease of operation decreases
Solution Approach 1:
The interconnect logic serves as a mediator that shields master logic units from deadlock avoidance constraints. Master logic units can operate freely issuing transactions with various identifiers, while the interconnect logic independently manages reordering safety, thus maintaining master logic unit flexibility while ensuring system reliability
Data Source
AI summary
An interconnect logic and method are provided for controlling transaction reordering by slave logic units coupled to the interconnect logic. The interconnect logic couples master logic units and slave logic units to enable transactions to be performed, each transaction having a transaction identifier associated therewith. ID aliasing logic is associated with at least a subset of slave logic units, with each slave logic unit in that at least a subset being able to issue response transfers for different transactions out of order with respect to the order of receipt by that slave logic unit of the address transfers of those transactions. For at least a subset of the transactions, if the slave logic unit involved in that transaction is associated with the ID aliasing logic, the ID aliasing logic is operable to replace the transaction identifier for that transaction with a predetermined identifier and then to forward the address transfer of the transaction along with that predetermined identifier to the slave logic unit. For any transactions that have their transaction identifier replaced with the predetermined identifier, the slave logic unit will not then perform any reordering since the same identifier, namely the predetermined identifier, is associated with each of those transactions. For any response transfer issue by the slave logic unit with the predetermined identifier, the ID aliasing logic replaces that predetermined identifier with the original transaction identifier removed previously so as to enable the routing of that data transfer via the interconnect logic to the appropriate master logic unit. This provides a very simple and effective mechanism for reducing the occurrence of a deadlock within the interconnect logic.