Semiconductor Interconnect Insert Layer for Low-Capacitance BEOL Routing
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Solution Overview
Problem
The increasing complexity and shrinking feature size of integrated circuits (ICs) lead to challenges in forming interconnect structures during the back-end-of-line (BEOL) processes, including higher aspect ratios, resistivity, and line-to-line capacitance, as well as issues like voids, collapse, and bending during patterning and deposition.
Innovation Solution
Incorporating an insert layer with a higher Young's modulus than the IMD layer between the CESL and IMD layers, or embedding it within the IMD layer, to enhance the structural strength and reduce the dielectric constant, thereby mitigating issues like collapsing and bending during patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If copper-based interconnect structures are implemented in multilayer interconnect features with ever-shrinking IC feature size, then functional density increases, but performance, yield, and cost challenges arise due to higher aspect ratios, resistivity, and line-to-line capacitance
Solution Approach 1:
A low-k dielectric layer is introduced as an intermediary between the interconnect lines, serving as a mediator to reduce line-to-line capacitance and improve signal integrity. This intermediate layer addresses the performance degradation caused by direct proximity of shrinking interconnect features.
Solution Approach 2:
The interconnect structure employs composite materials including copper for high conductivity, low-k dielectric materials for capacitance reduction, and various barrier and adhesion layers. This multi-material approach optimizes electrical performance while managing the challenges of miniaturization.
2Productivity
If interconnect features are scaled down to increase functional density, then production efficiency improves, but voids, collapse, and bending occur during patterning and deposition
Solution Approach 1:
Mandrel structures and spacer layers are formed in advance before the final interconnect patterning. These preliminary structures serve as templates and support during subsequent deposition and etching processes, preventing collapse and bending of the shrinking interconnect features.
Solution Approach 2:
Thin film structures including dielectric layers and barrier films are carefully engineered to provide mechanical support and flexibility to the shrinking interconnect features, preventing void formation and structural collapse during manufacturing processes.
3Length of moving object
If multilayer interconnect features become more compact, then IC feature size decreases, but line-to-line capacitance increases causing performance degradation
Solution Approach 1:
Low-k dielectric layers are positioned between adjacent interconnect lines to act as intermediaries that reduce capacitive coupling. This intermediary layer physically separates the conductors and reduces the harmful electric field interactions that cause signal interference and delay.
4Temperature
If interconnect structures are formed with higher aspect ratios, then vertical integration increases, but resistivity and manufacturing difficulty increase
Solution Approach 1:
The aspect ratios of vias and trenches are optimized by adjusting dimensional parameters within design constraints. Additionally, conductive fill materials and barrier layer properties are modified to reduce resistivity effects in high aspect ratio structures, balancing vertical integration with electrical performance.
Data Source
AI summary
A method of an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.