Interconnect Integrated Device for High-Density Substrate Routing
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Solution Overview
Problem
There is a challenge in fabricating small packages with high-density interconnects, as existing technologies struggle to accommodate high pin counts and compact form factors while maintaining efficient electrical paths and reducing routing congestion and inductance.
Innovation Solution
A package design that includes a substrate with interconnects and an interconnect integrated device, which provides a high-density electrical path between integrated devices, allowing for a compact form factor with improved capacitance density and reduced inductance by using a substrate with a dielectric layer and interconnects with a lower minimum pitch than the substrate, enabling higher I/O pin counts without increasing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a substrate with high-density interconnects is used to accommodate high pin counts, then the I/O pin count increases, but the package size and routing congestion increase
Solution Approach 1:
The patent introduces an interconnect integrated device that routes signals through the substrate thickness (z-dimension) rather than only across the substrate surface (x-y plane). This vertical routing dimension allows high pin counts to be achieved without proportionally increasing the package footprint, as signals can travel through multiple layers and surfaces of the substrate.
Solution Approach 2:
The substrate is divided into functional regions with different interconnect densities. The interconnect integrated device segments the routing function, with some interconnects providing high-density connections on one surface while other interconnects provide connections on opposite surfaces, allowing different areas to serve different purposes without all requiring maximum density.
2Device complexity
If traditional substrate routing is used, then the package structure is simple, but the inductance and routing congestion increase
Solution Approach 1:
By routing signals through the substrate thickness rather than only across the surface, the patent creates shorter effective signal paths and multiple routing options. This reduces inductance by minimizing the loop area and providing alternative current paths, while the added complexity is confined to the internal substrate structure rather than the overall package architecture.
Solution Approach 2:
The interconnect integrated device acts as an intermediary layer between integrated devices mounted on opposite surfaces of the substrate. It provides dedicated high-density interconnect paths that mediate signal transmission, reducing the inductance that would otherwise result from longer, more congested routing paths through the substrate.
3Reliability
If the substrate interconnect density is increased to reduce inductance, then the inductance decreases, but the manufacturing complexity and routing congestion increase
Solution Approach 1:
The substrate is designed with non-uniform interconnect density - high-density interconnect regions are localized to specific areas where they are most needed (such as near integrated devices), while other regions maintain lower density. This allows inductance reduction in critical paths without requiring uniform high-density interconnects throughout the entire substrate, simplifying manufacturing.
Solution Approach 2:
The interconnect structure is segmented into different density zones and functional regions. The interconnect integrated device separates high-density routing functions from lower-density interconnect regions, allowing each region to be optimized for its specific function while using manufacturing processes appropriate to its density requirements.
Data Source
AI summary
A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.