Interconnect Interface Unit for Master Device Adaptation
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Solution Overview
Problem
Data engines, with reduced hardware capabilities, face challenges in connecting to interconnect circuitry as master devices due to the need for specific interconnect protocols and high hardware requirements for interface mechanisms, limiting their flexibility and cost-effectiveness.
Innovation Solution
A data processing apparatus with a main controller executing programmable transaction sequences and an interconnect interface unit featuring queues and an interface controller, allowing the data engine to communicate with interconnect circuitry as a master device with minimal hardware, and flexibility to adapt to various interconnect protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a data engine is connected to interconnect circuitry with full interconnect protocol support, then it can operate as a master device, but the hardware complexity and cost increase significantly
Solution Approach 1:
The patent introduces an intermediary translation layer that converts simple data engine requests into full interconnect protocol transactions. This mediator handles protocol compliance, routing, and control signals, allowing the data engine to operate as a master device without requiring complex native protocol support in the data engine itself.
Solution Approach 2:
The patent creates a simplified copy of the interconnect interface within the data processing apparatus that mimics essential interconnect functionality. This copy handles basic transaction initiation and response reception, while full protocol compliance is managed separately, reducing the hardware burden on the data engine.
2Reliability
If dedicated interconnect interface hardware is provided in the data engine, then protocol compliance is ensured, but the cost and hardware resources increase
Solution Approach 1:
The patent implements a universal interface controller that can handle multiple interconnect protocols and transaction types through software configuration rather than dedicated hardware for each protocol. This multi-functional approach ensures protocol compliance while minimizing hardware resources by using a single adaptable interface unit.
Solution Approach 2:
The patent uses parameter-based configuration where the interface behavior is controlled by programmable parameters and control signals rather than fixed hardware logic. This allows the same hardware structure to adapt to different protocol requirements by changing operational parameters, maintaining reliability without increasing hardware complexity.
3Device complexity
If the data engine uses software-controlled general purpose pins to generate protocol signals, then hardware requirements are reduced, but the speed and reliability of protocol compliance decrease
Solution Approach 1:
The patent segments the interface functionality into two parts: a minimal hardware layer that provides essential signal generation and timing control, and a software layer that manages protocol-specific logic. This segmentation allows most protocol compliance to be handled by software on general purpose pins while hardware ensures timing-critical signals meet speed requirements.
Solution Approach 2:
The patent implements self-service mechanisms where the data engine's existing control and status registers are used to generate and manage interconnect protocol signals directly, without requiring separate dedicated interface hardware. The data engine itself services the protocol compliance functions through its existing control infrastructure, reducing additional hardware requirements while maintaining acceptable performance.
Data Source
AI summary
A data processing apparatus has a main controller for executing a programmable sequence of instructions including a transaction sequence of instructions used to process a transaction to be initiated by the data processing apparatus. The transaction sequence of instructions is programmed dependent on the interconnect protocol. The data processing apparatus has an interconnect interface unit including a plurality of queues with at least one send queue for issuing outbound payload information to the interconnect circuitry, and at least one receive queue for receiving inbound payload information from the interconnect circuitry. An interface controller is provided for pushing the outbound payload information on to the at least one send queue and popping the inbound payload information from the at least one receive queue, under the control of commands issued by the main controller. The interconnect interface unit has an interconnect port for communicating with the interconnect circuitry.