Interconnect Layer Resin Selection for Electronic Device Cost Reduction

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Solution Overview

Problem

The existing manufacturing method for electronic devices restricts the use of resins with lower decomposition temperatures in the interconnect layer on the solder ball side, limiting cost reduction due to the need for resins suitable for micromachining on the electronic component side.

Innovation Solution

The method involves forming a first interconnect layer on a supporting substrate, removing the substrate, and then forming a second interconnect layer that extends beyond the first layer, allowing the use of resins with lower decomposition temperatures for the second layer, enabling the use of suitable resins for micromachining on the electronic component side while using low-cost resins on the solder ball side.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If resin suitable for micromachining is used in the interconnect layer on the electronic component side, then micromachining precision is improved, but manufacturing cost increases

Engineering Contradiction:
Improvemicromachining precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies different resin types to different regions of the interconnect structure. The first interconnect layer (on the electronic component side) uses resin suitable for micromachining to ensure precision, while the second interconnect layer (on the solder ball side) uses lower-cost resin. This local differentiation resolves the contradiction by providing high precision where needed while reducing overall manufacturing cost.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If resin with lower decomposition temperature is used in the interconnect layer on the solder ball side, then manufacturing cost is reduced, but the ability to perform micromachining is lost

Engineering Contradiction:
Improvemanufacturing costVSAvoidmicromachining capability
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the interconnect structure into two separate layers formed at different stages. The first interconnect layer is formed on the supporting substrate where micromachining is performed using high-precision resin. After substrate removal, the second interconnect layer is formed using lower-cost resin. This segmentation allows each layer to use resin optimized for its specific function, resolving the contradiction between cost and micromachining capability.

Inventive Principle:
Principle #1Segmentation

3Stability of the object's composition

If the multilayer interconnect layer is formed by laminating interconnect layers in order on the supporting substrate, then structural integrity is maintained, but resin selection is restricted

Engineering Contradiction:
Improvestructural integrityVSAvoidresin selection flexibility
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent inverts the conventional lamination sequence. Instead of forming all interconnect layers in order on the supporting substrate, it first forms the first interconnect layer on the substrate, removes the substrate, and then forms the second interconnect layer. This inversion liberates resin selection for the second layer from the constraints of substrate-based processing, allowing use of lower-cost resins while maintaining structural integrity through the build-up construction.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS10879227B2Electronic device
Publication Date: 2020.12.29 RENESAS ELECTRONICS CORP
  • US10879227B2 patent drawing
  • US10879227B2 patent drawing
  • US10879227B2 patent drawing

AI summary

In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.