Interconnect Layer Stress Management in 3D NAND
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Solution Overview
Problem
The increase in stress due to the stacked body in semiconductor memory devices leads to warpage of the support substrate, potentially causing electrical discontinuity and manufacturing issues such as wafer breakage and abnormal chucking during processing.
Innovation Solution
The semiconductor memory device incorporates an interconnect layer with a core film having tensile stress, an intermediate film with compressive stress, and a first conductive film, which are sequentially formed and then simultaneously removed using CMP, thereby relaxing internal stress and reducing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked body of electrode layers is formed on the substrate, then the memory device functionality is achieved, but stress increases causing substrate warpage
Solution Approach 1:
The interconnect layer is segmented into multiple functional films: a core film (first conductive film) for electrical connection, an intermediate film (insulating film) for stress management, and a cap film (second conductive film) for stress compensation. This segmentation allows each layer to perform its specific function while collectively reducing substrate warpage
Solution Approach 2:
The interconnect layer uses a composite structure combining conductive materials (tungsten, copper) and insulating materials (silicon oxide, silicon nitride) in specific sequences. This composite structure enables both electrical functionality and stress control, as the different materials have different stress characteristics that can be balanced
2Stability of the object's composition
If stress compensation films are added to reduce warpage, then substrate stability is improved, but device complexity increases
Solution Approach 1:
The intermediate insulating film serves multiple functions: it provides electrical insulation between conductive layers, manages stress through its material properties, and contributes to the overall structural integrity. This multi-functionality reduces the need for additional dedicated stress compensation layers
3Stability of the object's composition
If complex thickness control is implemented for stress management, then warpage is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes specific parameter ranges for each film thickness (e.g., core film: 50-200 nm, intermediate film: 50-150 nm, cap film: 50-200 nm) to achieve stress balance. By defining specific parameter ranges rather than requiring precise single-value control, the manufacturing process becomes more robust while still achieving warpage reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces stress in the interconnect layer, preventing electrical discontinuity and manufacturing issues, while also simplifying the manufacturing process and reducing costs by eliminating the need for complex thickness control and additional processing steps.
Implementation Method 1
an interconnect layer with a core film having tensile stress, an intermediate film with compressive stress, and a first conductive film, which are sequentially formed and then simultaneously removed using CMP, thereby relaxing internal stress and reducing warpage
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a semiconductor film extending in stacking direction of the stacked body; an interconnect layer extending in the stacking direction of the stacked body and a first direction crossing the stacking direction; and an insulating film. The interconnect layer includes: a core film extending in the stacking direction and the first direction; an intermediate film provided integrally between the core film and the plurality of electrode layers and between the core film and the substrate; and a first conductive film provided integrally between the intermediate film and the plurality of electrode layers and between the intermediate film and the substrate, being in contact with the substrate, and having an upper surface flush with an upper surface of the intermediate film.