Interconnect Layout for Deep Trench Capacitor Plasma Arcing
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing burn-out and circuit shorts during the deposition of under bump metallizations (UBMs) due to plasma arcing, which can damage deep trench capacitors (DTCs) and affect capacitor density and yield.
Innovation Solution
The formation of a doped region in the substrate and a specific interconnect structure layout that includes a seal ring structure electrically coupled to the rest of the interconnect structure, reducing resistivity and preventing charge accumulation, thereby avoiding burn-out and shorts during the deposition process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If plasma deposition is used to form under bump metallizations, then deposition efficiency is improved, but plasma arcing causes burn-out and circuit shorts in deep trench capacitors
Solution Approach 1:
A doped region is formed in the substrate prior to the plasma deposition process. This doped region serves as a preliminary protective structure that provides a low-resistivity path for plasma current, preventing charge accumulation and eliminating the need for redesigning the capacitor structure itself. The preliminary action resolves the contradiction by preparing the substrate in advance to withstand plasma arcing.
Solution Approach 2:
The doped region acts as an intermediary between the plasma deposition process and the deep trench capacitor. It provides a controlled low-resistivity path that mediates the plasma current, preventing direct arcing into the capacitor structures. This intermediary structure enables continued use of plasma deposition while protecting the capacitors from damage.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then component integration is improved, but plasma arcing damage becomes more severe
Solution Approach 1:
The doped region is selectively formed in specific areas of the substrate where plasma arcing is most likely to occur and cause damage to capacitors. This local modification of electrical properties provides targeted protection without affecting the overall miniaturization and integration density of the device. The local quality change resolves the contradiction by protecting vulnerable areas while maintaining small feature sizes elsewhere.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the risk of burn-out and shorts in DTCs, enhancing capacitor density and improving semiconductor device yield by providing a low-resistivity path for current flow and minimizing voltage drops across critical components.
Implementation Method 1
The doped region in the substrate and the interconnect structure layout reduce resistivity and provide a low-resistivity path for current flow
Implementation Method 2
plasma arcing during a deposition step for forming under bump metallizations (UBMs)
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.