Interconnect Structure Layout for Stress-Resistant 3DIC Packaging

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Solution Overview

Problem

The semiconductor industry faces challenges in creating smaller, more reliable packaging techniques for semiconductor devices as they advance, particularly in managing high thermal and mechanical stress and reliability risks in stacked semiconductor devices like 3DICs, where traditional packaging methods may lead to cracking and delamination issues.

Innovation Solution

The implementation of interconnect structures with ground-up connector coupling regions in high-stress areas and non-ground-up regions in packaged semiconductor devices, utilizing dielectric layers, conductive layers, and underball metallization to enhance mechanical and thermal robustness, and incorporating redistribution layers for improved electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional packaging methods are used in stacked semiconductor devices, then manufacturing simplicity is maintained, but reliability deteriorates due to cracking and delamination under high thermal and mechanical stress

Engineering Contradiction:

ImprovereliabilityVSAvoidpackaging structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different connector coupling region configurations to different locations on the semiconductor device. Ground-up connector coupling regions are implemented in high-stress areas (such as corners) while non-ground-up regions are used in lower-stress areas. This local differentiation optimizes reliability where needed without unnecessarily complicating the entire packaging structure.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The connector coupling regions are segmented into distinct types (ground-up and non-ground-up) based on stress requirements. This segmentation allows the packaging structure to address high-stress areas specifically while maintaining simplicity in other regions, thus improving overall reliability without uniform complexity increase.

Inventive Principle:

Principle #1Segmentation

2Reliability

If ground-up connector coupling regions are implemented in high-stress areas, then reliability is improved by reducing cracks and delamination, but manufacturing complexity increases

Engineering Contradiction:

ImprovereliabilityVSAvoidmanufacturing ease

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Ground-up connector coupling regions are selectively implemented only in high-stress areas such as corners and edges, rather than across the entire device. This localized approach improves reliability where it is most needed while minimizing the additional manufacturing complexity, as not all regions require the more complex ground-up structure.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The connector coupling regions are designed and prepared in advance during the packaging process, with ground-up regions pre-formed in high-stress areas. This preliminary action allows the stress-resistant structure to be in place before thermal and mechanical stresses occur during operation, preventing cracks and delamination without requiring complex post-manufacturing interventions.

Inventive Principle:

Principle #10Preliminary action

3Volume of moving object

If stacked semiconductor devices are used to reduce physical size, then miniaturization is achieved, but thermal and mechanical stress increases leading to cracking and delamination

Engineering Contradiction:

Improvephysical sizeVSAvoidthermal and mechanical stress

Core Design Contradiction:

Volume of moving objectVSStress or pressure

Solution Approach 1:

The patent implements ground-up connector coupling regions specifically in high-stress areas such as corners and edges of stacked semiconductor devices. These localized reinforcement regions provide enhanced stress resistance where thermal and mechanical stresses are most concentrated, allowing miniaturization to proceed while protecting critical areas from cracking and delamination.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The connector coupling structure uses composite construction with ground-up regions providing stress resistance and non-ground-up regions maintaining electrical connectivity. This composite approach allows the packaging to handle high thermal and mechanical stresses in stacked devices while maintaining the miniaturized form factor, as the ground-up regions act as stress-dissipating elements within the overall connector structure.

Inventive Principle:

Principle #40Composite materials

Data Source

PatentUS20230307399A1Interconnect Structures, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

Publication Date: 2023.09.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.