Semiconductor Interconnect Layout With Sub-15 Nm End-to-End Spacing

The patent applies preliminary action by forming protrusions on the mask layer before the etching step. These protrusions are created through a tonal inversion process where a first etch removes material to form trenches, sacrificial material is deposited and planarized, then a second etch removes additional mask material to create the protrusions. This preliminary formation of protrusions enables the subsequent etch to directly transfer the reduced spacing pattern to the interconnect layer without requiring additional masking steps, thereby reducing fabrication complexity while achieving reduced end-to-end spacing.

The patent merges multiple functions into the existing mask layer and etching process. The tonal inversion process combines the formation of trenches, deposition of sacrificial material, planarization, and creation of protrusions all within the same mask layer structure. This merging allows the single mask layer to simultaneously define both the interconnect positions and the reduced spacing, eliminating the need for separate masking steps that would otherwise be required to achieve reduced end-to-end spacing, thus increasing packing density without increasing device complexity.

The patent applies inversion by using a tonal inversion process that creates protrusions instead of the conventional approach of creating only trenches or openings. The process inverts the typical pattern transfer by first forming trenches, then filling with sacrificial material, and finally removing portions of the mask layer to create protrusions that extend beyond the original trench boundaries. This inverted approach allows the etch to transfer a reduced spacing pattern to the interconnect layer, achieving manufacturing precision for reduced end-to-end spacing while keeping the fabrication process relatively simple by using the same mask layer.