Interconnect Layout Using Dummy Metal to Control Interposer Warpage
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Solution Overview
Problem
The warpage of interposers due to stress from interconnection layers in semiconductor packages causes defects during the attachment of wafers, leading to manufacturing challenges and reliability issues in semiconductor packaging.
Innovation Solution
A method of designing an interconnect structure with sequentially stacked interconnection layers, including dummy metal patterns and main metal patterns, where the layout of dummy metal patterns is determined based on the layout and number of interconnection layers to adjust metal density and control warpage, thereby minimizing stress-induced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnection layers are added to electrically connect semiconductor devices, then electrical connectivity is improved, but stress-induced warpage of the interposer increases
Solution Approach 1:
The patent applies local quality by varying the density distribution of dummy metal patterns in different regions of the interconnection layer. Specifically, higher density dummy patterns are placed in regions experiencing greater stress to locally compensate for warpage, while lower density is used in regions with less stress. This localized adjustment of metal density allows the interposer to maintain flatness while preserving electrical connectivity functionality.
Solution Approach 2:
The patent changes the physical parameters of the interconnection structure by adjusting the density, area, and distribution of dummy metal patterns. By modifying these parameters, the overall stress balance in the interconnection layer is altered, which compensates for the stress induced by functional interconnection layers and reduces interposer warpage while maintaining electrical connectivity.
2Shape
If dummy metal patterns are added to control warpage, then interposer flatness is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the warpage control function with the existing interconnection layer structure by integrating dummy metal patterns into the same layer. Instead of adding separate compensation structures, the dummy patterns are combined with the interconnection layers, allowing simultaneous achievement of electrical connectivity and warpage control without significantly increasing manufacturing complexity.
Solution Approach 2:
The patent uses dummy metal patterns that are copies or replicas of actual metal patterns in terms of geometry and material properties. These copied patterns are strategically placed to provide stress compensation without requiring new manufacturing processes, as they can be formed using the same photolithography and metal deposition steps as the functional interconnections.
Data Source
AI summary
A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.