Interconnect Liner Cleansing After Subtractive Etch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in selectively removing metal residues and liners from interconnect structures during the post-subtractive etch stage, which can lead to contamination and damage to dielectric layers, especially as feature sizes shrink.
Innovation Solution
A method involving a deposition stack with specific layers such as a substrate, dielectric layer, liner layer, etch stop layer, cap layer, and hard mask layer, where the hard mask is patterned and etched to form metal lines, followed by selective wet etching to remove liner residues without undercutting dielectric layers, and a hydrogen anneal process to cleanse metal oxides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching techniques are used to pattern interconnect structures, then metal lines can be formed, but metal residues and liner residues remain on the sidewalls causing contamination and potential damage to dielectric layers
Solution Approach 1:
The etching process is divided into two distinct stages: a first etch process that patterns the metal interconnect structures, and a second selective etch process that specifically removes liner residues from sidewalls. This segmentation allows each process to be optimized for its specific function, achieving both pattern accuracy and residue removal without compromising the dielectric layers.
Solution Approach 2:
A liner layer is introduced as an intermediary between the metal interconnect and the dielectric layer. This liner layer serves as a sacrificial material that protects the dielectric layer during etching and can be selectively removed afterward, preventing direct contact between etchants and the dielectric layer, thus avoiding contamination and damage.
2Productivity
If feature sizes are reduced to continue scaling, then device density increases, but the risk of etch damage to dielectric layers increases
Solution Approach 1:
The liner layer is deposited beforehand on the dielectric layer surface before metal interconnect formation. This pre-established protective layer acts as a cushion during subsequent etching processes, absorbing the impact of etchants and preventing direct damage to the dielectric layer, which is critical when working at reduced feature sizes where etch margins are tighter.
3Object-generated harmful factors
If aggressive etching is used to completely remove liner material, then sidewalls are cleaned, but the dielectric layer may be undercut or damaged
Solution Approach 1:
The second etch process is designed with local selectivity, targeting specifically the liner material on sidewalls while being selective against the dielectric layer. By adjusting etch parameters such as chemistry composition, temperature, and power, the process achieves localized removal of liner residues without affecting the underlying dielectric layer, maintaining its structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively removes metal residues and liners from semiconductor interconnects, preventing contamination and damage to dielectric layers, while maintaining the integrity of the metal lines and dielectric materials, even at smaller feature sizes.
Implementation Method 1
a second wet etch process can then be performed to remove the liner layer
Implementation Method 2
a hydrogen anneal process can be performed to cleanse any metal oxides
Data Source
AI summary
Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.