Interconnect Metal Liner Formation with SAM-Blocked Via Bottoms
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Solution Overview
Problem
As transistors and interconnects scale to the 3 nm node and beyond, increasing via resistance in interconnects leads to reduced performance and increased power consumption due to the high resistivity of barrier layers and challenges in selectively growing metal liners on via sidewalls rather than bottoms.
Innovation Solution
A method involving the selective deposition of a self-assembled monolayer (SAM) on the via bottom, followed by a barrier layer and a metal liner on the sidewalls, with the SAM being removed post-deposition to minimize via bottom metal liner growth and enhance selectivity, thereby reducing via resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is deposited on via sidewalls to prevent copper diffusion, then adhesion and diffusion prevention are improved, but via resistance increases due to high resistivity of the barrier layer
Solution Approach 1:
The patent segments the via structure into distinct regions: a first portion with a barrier layer for adhesion and diffusion prevention, and a second portion with a metal liner for low-resistance current conduction. This segmentation allows each layer to optimize its function without compromise.
Solution Approach 2:
Different materials and thicknesses are applied to different locations within the via structure. The barrier layer is present on sidewalls for adhesion, while the metal liner is selectively thicker on the bottom to reduce contact resistance, creating local quality variations that address different functional requirements.
2Object-affected harmful factors
If metal liner thickness on sidewalls is increased to reduce via resistance, then via resistance decreases, but deposition selectivity between sidewalls and bottom becomes more difficult to control
Solution Approach 1:
A self-assembled monolayer is deposited on the via bottom before the metal liner deposition step. This preliminary action creates a selective surface that directs metal liner growth preferentially on sidewalls while limiting bottom growth, enabling precise thickness control through the deposition process itself.
Solution Approach 2:
The self-assembled monolayer acts as an intermediary between the via bottom surface and the metal liner deposition process. It mediates the deposition behavior by providing selective binding sites that control where metal atoms nucleate and grow, achieving the desired thickness distribution.
3Object-affected harmful factors
If barrier layer thickness is reduced to decrease via resistance, then via resistance decreases, but adhesion and diffusion prevention capability deteriorates
Solution Approach 1:
The protective and conductive functions are segmented into different layers: the barrier layer handles adhesion and diffusion prevention, while the metal liner handles low-resistance conduction. This allows the barrier layer to be thin without compromising adhesion, as its primary protective function is maintained.
Solution Approach 2:
The via structure uses a composite material system combining a barrier layer (for adhesion and diffusion barrier) with a metal liner (for low-resistance conduction). This composite approach leverages the strengths of different materials to simultaneously achieve adhesion, diffusion prevention, and low resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces via resistance by at least 20% and improves deposition selectivity, allowing for thinner or no metal growth on the via bottom while maintaining growth on the sidewalls, thus enhancing interconnect performance.
Implementation Method 1
selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap
Implementation Method 2
selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap
Data Source
AI summary
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM has a general formula I to XIX, wherein R, R′, R1, R2, R3, R4, and R5 are independently selected from hydrogen (H), alkyl, alkene, alkyne, and aryl, n is from 1 to 20, m is from 1 to 20, x is from 1 to 2, and y is from 1 to 2. A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.